Presentations
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Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts
Short video for Intel Hardware Security Academic Award Finalist, August 2024.
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Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors
Presented at KTH, Stockholm, Sweden, February 2024.
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Leveraging LLVM’s ScalarEvolution for Symbolic Data Cache Analysis
Presented at RTSS, Taipei, Taiwan, November 2023.
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Fast, Accurate, and Interpretable Basic-Block Throughput Prediction
Presented at the IEEE International Symposium on Workload Characterization in Ghent, Belgium, October 2023.
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Verifying the Security of Microarchitectures based on Hardware-Software Contracts
Presented at the Workshop of the Intel Scalable Assurance Academic Research Cluster in Hillsboro, USA, September 2022.
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Warping Cache Simulation of Polyhedral Programs
Presented at PLDI in San Diego, USA, June 2022. Video is available here.
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Hardware-Software Contracts for Secure Speculation
Presented at Intel IPAS Tech Sharing Talk in March 2022.
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Provably Timing-Predictable Microarchitectures
Presented at the Colloque GDR SoC in June 2021.
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Hardware-Software Contracts for Safe and Secure Systems
Presented at Huawei Systems Software Innovations Summit 2021 and in the InvasIC Seminar in July 2021.
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Hardware-Software Contracts for Secure Speculation
Presented at German IOI (International Olympiad in Informatics) training camp in June 2020.
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Cache Persistence Analysis: Finally Exact
Received the Best Presentation Award at RTSS 2020. Video is available here.
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Spectector: Principled detection of speculative information flows
Presented at Northeastern University, Boston, USA, at Forschungstage Informatik 2019, Max Planck Institute for Informatics, Germany, at the Summer School on the Security of Software / Hardware Interfaces 2019, Rennes, France, at Verimag, Grenoble, France, and in the Joint Lecture Series at Saarland Informatics Campus, 2020.
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SIC: Provably Timing-Predictable Strictly In-Order Pipelined Processor Core
Presented at RTSS 2018, Nashville, USA.
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Write-back Caches in WCET Analysis
Presented at ECRTS 2017, Dubrovnik, Croatia.
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Challenges for Timing Analysis of Multi-Core Architectures
Presented at DICE-FOPARA 2017, Uppsala, Sweden.
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Timing Predictability and How to Achieve It
Presented at Dagstuhl Seminar 16441 "Adaptive Isolation for Predictability and Security", 2016, Wadern, Germany.
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Enabling Compositionality for Multicore Timing Analysis
Presented at Verimag, 2016, Grenoble, France.
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Sichere Zukunftsvorhersagen durch Modellierung und Approximation (German only)
Presented at Forschungstage Informatik 2016, Max Planck Institute for Informatics, Germany.
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Timing Anomalies and Timing Compositionality
Presented at TACLe Meeting at HIPEAC, 2016, Prague, Czech Republic.
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On the Smoothness of Paging Algorithms
Presented at TU Dortmund, Germany, 2016, WAOA, 2015, Patras, Greece.
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ASTRA: A Tool for Abstract Interpretation of Graph Transformation Systems
Presented at SPIN, 2015, Stellenbosch, South Africa.
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Architecture-Parametric Timing Analysis
Presented at RTAS, 2014, Berlin, Germany.
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Selfish-LRU: Preemption-Aware Caching for Predictability and Performance
Presented at RTAS, 2014, Berlin, Germany.
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Challenges for
Worst-case Execution Time Analysis of
Multi-core Architectures
Presented at Intel Braunschweig, 2013, Germany.
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Learning Cache Models by Measurements, pdf version
Presented at Uppsala University, 2012, Uppsala, Sweden.
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PRET DRAM controller: Bank Privatization for Predictability and Temporal Isolation
Presented at the Embedded Systems Week, 2011, Taipei, Taiwan and Verimag, Grenoble, France.
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To Meet or Not to Meet the Deadline
Presented at the Ninth Biennial Ptolemy Miniconference, 2011, Berkeley, CA.
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Caches in WCET Analysis -- Predictability, Competitiveness, Sensitivity
PhD defense talk, also at TRESOR seminar, Ecole Polytechnique Fédérale de Lausanne, HCDDES Web Conference, and at ARTIST Summer School in Europe 2009, Autrans, France (find recording here)
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Relative Competitive Analysis of Cache Replacement Policies
at LCTES 08
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Timing Predictability of Cache Replacement Policies
at AVACS Virtual Seminar (find recording here) and Dagstuhl Seminar on Quantitative Aspects of Embedded Systems
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Shape Analysis of Sets
at Trustworthy Software Workshop, Tel Aviv University, etc.
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Timing Anomalies
at WCET'06 Workshop, AVACS Meeting Oldenburg, etc.
