Jan Reineke

Real-Time and Embedded Systems Lab
Saarland University
Saarland Informatics Campus
Phone: +49 681 302 4448
eMail:
Building: E 1 3 Room: 410
Coordinates: N 49.257833° E 7.045144°

Administrative Assistant: Sandra Neumann
Phone: +49 681 302 3434
Building: E 1 3 Room: 430

Office Hour: Wednesday 16:00-17:00

I am looking for PhD students and postdocs to work on safety and security problems at the hardware-software interface!
Possible research topics are flexible and include but are not limited to:
  • Static program analysis of real-time and security properties
  • Design of timing-predictable microarchitectures
  • Design of secure microarchitectures
  • Formal verification of hardware w.r.t. hardware-software contracts
If you are interested, please feel free to . My work is generously supported by an ERC Advanced Grant.

I am always looking for student assistants.
If you are interested in working with me and my group or if you are looking for a Bachelor or Master thesis topic, please feel free to stop by my office or to drop me an email.

Short CV

Jan Reineke is a professor of computer science at Saarland University. Before joining Saarland University in 2012, he has been a postdoctoral scholar at UC Berkeley in the Ptolemy group from 2009 to 2011. He completed his MSc and PhD in Computer Science at Saarland University in 2005 and 2008, respectively, and his BSc in Computing Science at the University of Oldenburg in 2003.

His research centers around problems at the boundary between hardware and software.

In the area of real-time systems, he is particularly interested in principles for the design of timing-predictable hardware and in precise and efficient timing-analysis techniques for multi-core architectures. His recent results include the design of the first provably timing-predictable pipelined processor design (RTSS 2018) and the first exact analyses for LRU caches (CAV 2017, POPL 2019, RTSS 2019).

Another focus of his work are security vulnerabilities of hardware-software systems. Recent results include the development of automatic techniques to detect information leaks introduced by speculative execution (Spectector, S&P 2020), techniques to quantify the information leakage through cache side channels (ACM TISSEC 2015), and automatic methods to obtain highly detailed performance models for modern microarchitectures (uops.info, ASPLOS 2019).

In 2012, he was selected as an Intel Early Career Faculty Honor Program awardee. He was the PC chair of EMSOFT 2014, the International Conference on Embedded Software, a Topic co-chair at DATE 2016 and the PC chair of WCET 2017, the International Workshop on Worst-Case Execution Time Analysis. His papers have been awarded 7 outstanding paper awards and one best-paper nomination, most recently at Oakland (2021), RTSS (2018, 2019), and ECRTS (2017). In 2021, he has been awarded an ERC Advanced Grant.

Selected Recent Publications

Journal Papers

  1. Fast and Exact Analysis for LRU Caches
    V. Touzeau, C. Maïza, D. Monniaux, and J. Reineke
    Proc. ACM Program. Lang., 3(POPL), January 2019
    [doi] [bib]
  2. An extensible framework for multicore response time analysis
    R. Davis, S. Altmeyer, L. Indrusiak, C. Maiza, V. Nelis, and J. Reineke
    Real-Time Systems, 54(3), July 2018
    [doi] [bib]
  3. The Semantic Foundations and a Landscape of Cache-Persistence Analyses
    J. Reineke
    LITES, 5(1), 2018
    [doi] [bib]
  4. CacheAudit: A Tool for the Static Analysis of Cache Side Channels
    G. Doychev, B. Köpf, L. Mauborgne, and J. Reineke
    ACM Trans. Inf. Syst. Secur., 18(1), June 2015
    [doi] [pdf] [bib]
  5. Towards compositionality in execution time analysis: definition and challenges
    S. Hahn, J. Reineke, and R. Wilhelm
    SIGBED Review, 12(1), 2015
    [doi] [bib]

Conference and Workshop Papers

  1. uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
    A. Abel and J. Reineke
    ICS '22: 2022 International Conference on Supercomputing, Virtual Event, USA, June 27-30, 2022, 2022
    [bib]
  2. Warping Cache Simulation for Polyhedral Programs
    C. Morelli and J. Reineke
    PLDI, June 2022
    [doi] [bib]
  3. Hardware-Software Contracts for Secure Speculation (Best Paper Award award)
    M. Guarnieri, B. Köpf, J. Reineke, and P. Vila
    S&P (Oakland), May 2021
    [bib]
  4. SPECTECTOR: Principled Detection of Speculative Information Flows
    M. Guarnieri, B. Köpf, J. Morales, J. Reineke, and A. Sánchez
    S&P (Oakland), May 2020
    [pdf] [bib]
  5. uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
    A. Abel and J. Reineke
    ASPLOS, 2019
    [doi] [bib]
  6. Cache Persistence Analysis: Finally Exact (Best Paper Award award)
    G. Stock, S. Hahn, and J. Reineke
    RTSS, December 2019
    [bib]
  7. Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core (Best Student Paper Award award)
    S. Hahn and J. Reineke
    RTSS, December 2018
    [pdf] [pdf slides] [bib]
  8. Write-Back Caches in WCET Analysis (Outstanding Paper Award award)
    T. Blaß , S. Hahn, and J. Reineke
    ECRTS, 2017
    [doi] [pdf] [pdf slides] [bib]
  9. Abstract PRET Machines
    E. Lee, J. Reineke, and M. Zimmer
    RTSS, 2017
    [doi] [bib]
  10. MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy Machines
    A. Abel and J. Reineke
    ICCAD, 2015
    [doi] [pdf] [bib]

Publications

A list of all of my publications can be found here and on DBLP.

Recent and Upcoming Professional Activities