Hardware Design Seminar/Proseminar


Jan Reineke, Sebastian Hahn



In this seminar/proseminar you will learn about various aspects of modern microarchitectures, ranging from performance-enhancing features like pipelining and caches to the implementation of interrupts and virtual memory.

Groups of 2 to 3 students will form teams and collaborate to add a particular microarchitectural feature to a basic ARM processor design that will be provided by the organizers at the beginning of the semester.

The implementation will be carried out in the hardware description language Verilog/SystemVerilog. Thus besides learning about features of modern processors, you will also gain valuable practical skills that will enable you to create your own hardware designs and to program FPGAs!

List of Topics

Below you will find a list of suggested topics. If you are interested in implementing an aspect not listed below, please let us know! We are open to suggestions.

Modus Operandi

  1. Beginning of the term: Students choose topics and teams are formed.
  2. Reading of background material, mostly from textbooks, possibly from research papers, and initial experiments.
  3. Students work out a concrete project plan and identify challenges: first presentation of projects after 6 to 8 weeks.
  4. Implementation phase. An FPGA board will be provided for experimentation.
  5. Final project presentation at the end of the term:
    • 15-minute team presentation
    • 10-minute presentation by each team member discussing their contributions
    • Practical demonstration of project outcomes

The seminar can be taken both as a 7 credit-point seminar or as a 5 credit-point proseminar. The workload will then be adjusted accordingly.


If you would like to participate in this seminar, please send us an email in which you:


General Information: