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Edited

1. 17th International Workshop on Worst-Case Execution Time Analysis
   J. Reineke
   WCET, 2017
   [bib]

   @proceedings{Reineke17,
    title = {17th International Workshop on Worst-Case Execution Time Analysis},
    bibsource = {dblp computer science bibliography, http://dblp.org},
    biburl = {http://dblp.uni-trier.de/rec/bib/conf/wcet/2017},
    editor = {Reineke, Jan},
    isbn = {978-3-95977-057-6},
    publisher = {Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik},
    series = {{OASICS}},
    timestamp = {Mon, 26 Jun 2017 10:56:02 +0200},
    url = {http://www.dagstuhl.de/dagpub/978-3-95977-057-6},
    volume = {57},
    year = {2017}
   }
   

2. 2014 International Conference on Embedded Software
   T. Mitra and J. Reineke
   EMSOFT, 2014
   [doi] [bib]

   @proceedings{Mitra14,
    title = {2014 International Conference on Embedded Software},
    doi = {10.1145/2656045},
    editor = {Mitra, Tulika and Reineke, Jan},
    publisher = {{ACM}},
    url = {http://doi.acm.org/10.1145/2656045},
    year = {2014}
   }
   

Journal Papers

1. Type-aware Federated Scheduling for Typed DAG Tasks on Heterogeneous Multicore Platforms
   C. Lin, J. Shi, N. Ueter, M. Günzel, J. Reineke, and J. Chen
   IEEE Trans. Computers, 72(5), 2023
   [doi] [bib]

   @article{9869701,
    title = {Type-aware Federated Scheduling for Typed {DAG} Tasks on Heterogeneous Multicore Platforms},
    address = {Los Alamitos, CA, USA},
    author = {Lin, C. and Shi, J. and Ueter, N. and G\"unzel, M. and Reineke, J. and Chen, J.},
     journal      = {{IEEE} Trans. Computers},
     volume       = {72},
     number       = {5},
     pages        = {1286--1300},
     year         = {2023},
     url          = {https://doi.org/10.1109/TC.2022.3202748},
     doi          = {10.1109/TC.2022.3202748},
   }
   

2. On the Incomparability of Cache Algorithms in Terms of Timing Leakage
   P. Cañones, B. Köpf, and J. Reineke
   Logical Methods in Computer Science, 15(1), March 2019
   [doi] [pdf] [bib]

   @article{Canones19,
    title = {On the Incomparability of Cache Algorithms in Terms of Timing Leakage},
    author = {Ca\~nones, Pablo and K\"opf, Boris and Reineke, Jan},
    doi = {},
    journal = {{Logical Methods in Computer Science}},
    keyword = {Computer Science - Cryptography and Security},
    month = {Mar},
    number = {1},
    url = {https://lmcs.episciences.org/5253},
    volume = {15},
    year = {2019}
   }
   

3. Design and analysis of SIC: a provably timing-predictable pipelined processor core
   S. Hahn and J. Reineke
   Real-Time Systems, November 2019
   [doi] [bib]

   @article{Hahn2019b,
    title = {Design and analysis of {SIC}: a provably timing-predictable pipelined processor core},
    author = {Hahn, Sebastian and Reineke, Jan},
    day = {15},
    doi = {10.1007/s11241-019-09341-z},
    issn = {1573-1383},
    journal = {Real-Time Systems},
    month = {Nov},
    url = {https://doi.org/10.1007/s11241-019-09341-z},
    year = {2019}
   }
   

4. Basic problems in multi-view modeling
   J. Reineke, C. Stergiou, and S. Tripakis
   Software and Systems Modeling, 18(3), 2019
   [doi] [bib]

   @article{Reineke19,
    title = {Basic problems in multi-view modeling},
    author = {Reineke, Jan and Stergiou, Christos and Tripakis, Stavros},
    doi = {10.1007/s10270-017-0638-1},
    journal = {Software and Systems Modeling},
    number = {3},
    pages = {1577--1611},
    url = {https://doi.org/10.1007/s10270-017-0638-1},
    volume = {18},
    year = {2019}
   }
   

5. Fast and Exact Analysis for LRU Caches
   V. Touzeau, C. Maïza, D. Monniaux, and J. Reineke
   Proc. ACM Program. Lang., 3(POPL), January 2019
   [doi] [bib]

   @article{Touzeau19,
    title = {Fast and Exact Analysis for LRU Caches},
    acmid = {3290367},
    address = {New York, NY, USA},
    articleno = {54},
    author = {Touzeau, Valentin and Ma\"{\i }za, Claire and Monniaux, David and Reineke, Jan},
    doi = {10.1145/3290367},
    issn = {2475-1421},
    issue_date = {January 2019},
    journal = {Proc. ACM Program. Lang.},
    keyword = {Abstract Interpretation, Cache Analysis, LRU},
    month = {Jan},
    number = {POPL},
    numpages = {29},
    pages = {54:1--54:29},
    publisher = {ACM},
    url = {http://doi.acm.org/10.1145/3290367},
    volume = {3},
    year = {2019}
   }
   

6. Response-time analysis for fixed-priority systems with a write-back cache
   R. Davis, S. Altmeyer, and J. Reineke
   Real-Time Systems, April 2018
   [doi] [bib]

   @article{Davis18,
    title = {Response-time analysis for fixed-priority systems with a write-back cache},
    abstract = {This paper introduces analyses of write-back caches integrated into response-time analysis for fixed-priority preemptive and non-preemptive scheduling. For each scheduling paradigm, we derive four different approaches to computing the additional costs incurred due to write backs. We show the dominance relationships between these different approaches and note how they can be combined to form a single state-of-the-art approach in each case. The evaluation explores the relative performance of the different methods using a set of benchmarks, as well as making comparisons with no cache and a write-through cache. We also explore the effect of write buffers used to hide the latency of write-through caches. We show that depending upon the depth of the buffer used and the policies employed, such buffers can result in domino effects. Our evaluation shows that even ignoring domino effects, a substantial write buffer is needed to match the guaranteed performance of write-back caches.},
    author = {Davis, Robert I. and Altmeyer, Sebastian and Reineke, Jan},
    day = {11},
    doi = {10.1007/s11241-018-9305-z},
    issn = {1573-1383},
    journal = {Real-Time Systems},
    month = {Apr},
    url = {https://doi.org/10.1007/s11241-018-9305-z},
    year = {2018}
   }
   

7. An extensible framework for multicore response time analysis
   R. Davis, S. Altmeyer, L. Indrusiak, C. Maiza, V. Nelis, and J. Reineke
   Real-Time Systems, 54(3), July 2018
   [doi] [bib]

   @article{Davis18a,
    title = {An extensible framework for multicore response time analysis},
    abstract = {In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on context-independent WCET values. Instead, the analysis formulates response times directly from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.},
    author = {Davis, Robert I. and Altmeyer, Sebastian and Indrusiak, Leandro S. and Maiza, Claire and Nelis, Vincent and Reineke, Jan},
    day = {01},
    doi = {10.1007/s11241-017-9285-4},
    issn = {1573-1383},
    journal = {Real-Time Systems},
    month = {Jul},
    number = {3},
    pages = {607--661},
    url = {https://doi.org/10.1007/s11241-017-9285-4},
    volume = {54},
    year = {2018}
   }
   

8. Checking multi-view consistency of discrete systems with respect to periodic sampling abstractions
   M. Pittou, P. Manolios, J. Reineke, and S. Tripakis
   Science of Computer Programming, 167, 2018
   [doi] [bib]

   @article{Pittou2018,
    title = {Checking multi-view consistency of discrete systems with respect to periodic sampling abstractions},
    author = {Pittou, Maria and Manolios, Panagiotis and Reineke, Jan and Tripakis, Stavros},
    doi = {10.1016/j.scico.2018.07.003},
    issn = {0167-6423},
    journal = {Science of Computer Programming},
    keyword = {Multi-view modeling, View consistency, Formal methods, Modeling, Verification},
    pages = {1 - 24},
    url = {http://www.sciencedirect.com/science/article/pii/S0167642318302612},
    volume = {167},
    year = {2018}
   }
   

9. On the Smoothness of Paging Algorithms
   J. Reineke and A. Salinger
   Theory of Computing Systems, 62(2), February 2018
   [doi] [bib]

   @article{Reineke18,
    title = {On the Smoothness of Paging Algorithms},
    abstract = {We study the smoothness of paging algorithms. How much can the number of page faults increase due to a perturbation of the request sequence? We call a paging algorithm smooth if the maximal increase in page faults is proportional to the number of changes in the request sequence. We also introduce quantitative smoothness notions that measure the smoothness of an algorithm. We derive lower and upper bounds on the smoothness of deterministic and randomized demand-paging and competitive algorithms. Among strongly-competitive deterministic algorithms, LRU matches the lower bound, while FIFO matches the upper bound. Well-known randomized algorithms such as Partition, Equitable, or Mark are shown not to be smooth. We introduce two new randomized algorithms, called Smoothed-LRU and LRU-Random. Smoothed-LRU allows sacrificing competitiveness for smoothness, where the trade-off is controlled by a parameter. LRU-Random is at least as competitive as any deterministic algorithm but smoother.},
    author = {Reineke, Jan and Salinger, Alejandro},
    day = {01},
    doi = {10.1007/s00224-017-9813-6},
    issn = {1433-0490},
    journal = {Theory of Computing Systems},
    month = {Feb},
    number = {2},
    pages = {366--418},
    url = {https://doi.org/10.1007/s00224-017-9813-6},
    volume = {62},
    year = {2018}
   }
   

10. The Semantic Foundations and a Landscape of Cache-Persistence Analyses
    J. Reineke
    LITES, 5(1), 2018
    [doi] [bib]

    @article{Reineke18a,
     title = {The Semantic Foundations and a Landscape of Cache-Persistence Analyses},
     author = {Reineke, Jan},
     doi = {10.4230/LITES-v005-i001-a003},
     journal = {{LITES}},
     number = {1},
     pages = {03:1--03:52},
     url = {https://doi.org/10.4230/LITES-v005-i001-a003},
     volume = {5},
     year = {2018}
    }
    

11. A Survey on Static Cache Analysis for Real-Time Systems
    M. Lv, N. Guan, J. Reineke, R. Wilhelm, and W. Yi
    Leibniz Transactions on Embedded Systems, 3(1), 2016
    [doi] [pdf] [bib]

    @article{Lv16,
     title = {A Survey on Static Cache Analysis for Real-Time Systems},
     abstract = {Real-time systems are reactive computer systems that must produce their reaction to a stimulus within given time bounds. A vital verification requirement is to estimate the Worst-Case Execution Time (WCET) of programs. These estimates are then used to predict the timing behavior of the overall system. The execution time of a program heavily depends on the underlying hardware, among which cache has the biggest influence. Analyzing cache behavior is very challenging due to the versatile cache features and complex execution environment. This article provides a survey on static cache analysis for real-time systems. We first present the challenges and static analysis techniques for independent programs with respect to different cache features. Then, the discussion is extended to cache analysis in complex execution environment, followed by a survey of existing tools based on static techniques for cache analysis. An outlook for future research is provided at last.},
     author = {Lv, Mingsong and Guan, Nan and Reineke, Jan and Wilhelm, Reinhard and Yi, Wang},
     doi = {10.4230/LITES-v003-i001-a005},
     issn = {2199-2002},
     journal = {Leibniz Transactions on Embedded Systems},
     keyword = {Hard real-time; Cache analysis; Worst-case execution time},
     number = {1},
     pages = {05--1-05:48},
     url = {http://ojs.dagstuhl.de/index.php/lites/article/view/LITES-v003-i001-a005},
     volume = {3},
     year = {2016}
    }
    

12. CacheAudit: A Tool for the Static Analysis of Cache Side Channels
    G. Doychev, B. Köpf, L. Mauborgne, and J. Reineke
    ACM Trans. Inf. Syst. Secur., 18(1), June 2015
    [doi] [pdf] [bib]

    @article{Doychev15,
     title = {{CacheAudit}: A Tool for the Static Analysis of Cache Side Channels},
     acmid = {2756550},
     address = {New York, NY, USA},
     articleno = {4},
     author = {Doychev, Goran and K{\"o}pf, Boris and Mauborgne, Laurent and Reineke, Jan},
     doi = {10.1145/2756550},
     issn = {1094-9224},
     issue_date = {June 2015},
     journal = {ACM Trans. Inf. Syst. Secur.},
     keyword = {Side-channel attacks, caches},
     month = {Jun},
     number = {1},
     numpages = {32},
     pages = {4:1--4:32},
     publisher = {ACM},
     url = {http://doi.acm.org/10.1145/2756550},
     volume = {18},
     year = {2015}
    }
    

13. Towards compositionality in execution time analysis: definition and challenges
    S. Hahn, J. Reineke, and R. Wilhelm
    SIGBED Review, 12(1), 2015
    [doi] [bib]

    @article{Hahn15,
     title = {Towards compositionality in execution time analysis: definition and challenges},
     author = {Hahn, Sebastian and Reineke, Jan and Wilhelm, Reinhard},
     bibsource = {dblp computer science bibliography, http://dblp.org},
     biburl = {http://dblp.uni-trier.de/rec/bib/journals/sigbed/0001RW15},
     doi = {10.1145/2752801.2752805},
     journal = {{SIGBED} Review},
     number = {1},
     pages = {28--36},
     timestamp = {Sat, 25 Apr 2015 19:50:05 +0200},
     url = {http://doi.acm.org/10.1145/2752801.2752805},
     volume = {12},
     year = {2015}
    }
    

14. Building Timing Predictable Embedded Systems
    P. Axer, R. Ernst, H. Falk, A. Girault, D. Grund, N. Guan, B. Jonsson, P. Marwedel, J. Reineke, C. Rochange, M. Sebastian, R. Hanxleden, R. Wilhelm, and W. Yi
    ACM Trans. Embed. Comput. Syst., 13(4), March 2014
    [doi] [pdf] [bib]

    @article{Axer14,
     title = {Building Timing Predictable Embedded Systems},
     acmid = {2560033},
     address = {New York, NY, USA},
     articleno = {82},
     author = {Axer, Philip and Ernst, Rolf and Falk, Heiko and Girault, Alain and Grund, Daniel and Guan, Nan and Jonsson, Bengt and Marwedel, Peter and Reineke, Jan and Rochange, Christine and Sebastian, Maurice and Hanxleden, Reinhard Von and Wilhelm, Reinhard and Yi, Wang},
     doi = {10.1145/2560033},
     issn = {1539-9087},
     issue_date = {February 2014},
     journal = {ACM Trans. Embed. Comput. Syst.},
     keyword = {Embedded systems, predictability, resource sharing, safety-critical systems, timing analysis},
     month = {Mar},
     number = {4},
     numpages = {37},
     pages = {82:1--82:37},
     publisher = {ACM},
     url = {http://doi.acm.org/10.1145/2560033},
     volume = {13},
     year = {2014}
    }
    

15. Randomized Caches Considered Harmful in Hard Real-Time Systems
    J. Reineke
    Leibniz Transactions on Embedded Systems, 1(1), 2014
    [doi] [pdf] [bib]

    @article{Reineke14e,
     title = {Randomized Caches Considered Harmful in Hard Real-Time Systems},
     abstract = {We investigate the suitability of caches with randomized placement and replacement in the context of hard real-time systems. Such caches have been claimed to drastically reduce the amount of information required by static worst-case execution time (WCET) analysis, and to be an enabler for measurement-based probabilistic timing analysis. We refute these claims and conclude that with prevailing static and measurement-based analysis techniques caches with deterministic placement and least-recently-used replacement are preferable over randomized ones.},
     author = {Reineke, Jan},
     doi = {10.4230/LITES-v001-i001-a003},
     issn = {2199-2002},
     journal = {Leibniz Transactions on Embedded Systems},
     keyword = {real-time systems, caches, randomization, WCET analysis},
     number = {1},
     pages = {03:1-03:13},
     pdf = {http://ojs.dagstuhl.de/index.php/lites/article/view/LITES-v001-i001-a003/lites-v001-i001-a003-pdf},
     url = {http://ojs.dagstuhl.de/index.php/lites/article/view/LITES-v001-i001-a003},
     volume = {1},
     year = {2014}
    }
    

16. Sensitivity of cache replacement policies
    J. Reineke and D. Grund
    ACM Trans. Embed. Comput. Syst., 12(1s), March 2013
    [doi] [pdf] [bib]

    @article{Reineke13,
     title = {Sensitivity of cache replacement policies},
     acmid = {2435238},
     address = {New York, NY, USA},
     articleno = {42},
     author = {Reineke, Jan and Grund, Daniel},
     doi = {10.1145/2435227.2435238},
     issn = {1539-9087},
     issue_date = {March 2013},
     journal = {ACM Trans. Embed. Comput. Syst.},
     keyword = {Measurement-based timing analysis, WCET analysis, cache performance, predictability, replacement policy, worst-case execution time},
     month = {Mar},
     number = {1s},
     numpages = {18},
     pages = {42:1--42:18},
     publisher = {ACM},
     url = {http://doi.acm.org/10.1145/2435227.2435238},
     volume = {12},
     year = {2013}
    }
    

17. Branch Target Buffers: WCET Analysis Framework and Timing Predictability
    D. Grund, J. Reineke, and G. Gebhard
    Journal of Systems Architecture, 57(6), 2011
    [doi] [pdf] [bib]

    @article{Grund11b,
     title = {Branch Target Buffers: {WCET} Analysis Framework and Timing Predictability},
     author = {Grund, Daniel and Reineke, Jan and Gebhard, Gernot},
     doi = {10.1016/j.sysarc.2010.05.013},
     issn = {1383-7621},
     journal = {Journal of Systems Architecture},
     number = {6},
     pages = {625--637},
     url = {http://rw4.cs.uni-saarland.de/~grund/papers/jsa10-BTBs.pdf},
     volume = {57},
     year = {2011}
    }
    

18. Predictability Considerations in the Design of Multi-Core Embedded Systems
    C. Cullmann, C. Ferdinand, G. Gebhard, D. Grund, C. Maiza, J. Reineke, B. Triquet, S. Wegener, and R. Wilhelm
    Ingénieurs de l'Automobile, 807, September 2010
    [bib]

    @article{Cullmann10a,
     title = {Predictability Considerations in the Design of Multi-Core Embedded Systems},
     author = {Cullmann, Christoph and Ferdinand, Christian and Gebhard, Gernot and Grund, Daniel and Maiza, Claire and Reineke, Jan and Triquet, Beno\^\i t and Wegener, Simon and Wilhelm, Reinhard},
     issn = {0020-1200},
     journal = {Ing\'enieurs de l'Automobile},
     month = {Sep},
     pages = {36--42},
     volume = {807},
     year = {2010}
    }
    

19. Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-critical Embedded Systems
    R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand
    IEEE Transactions on CAD of Integrated Circuits and Systems, 28(7), July 2009
    [doi] [bib]

    @article{Wilhelm09,
     title = {Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-critical Embedded Systems},
     author = {Wilhelm, Reinhard and Grund, Daniel and Reineke, Jan and Schlickling, Marc and Pister, Markus and Ferdinand, Christian},
     doi = {10.1109/TCAD.2009.2013287},
     journal = {IEEE Transactions on {CAD} of Integrated Circuits and Systems},
     month = {Jul},
     number = {7},
     pages = {966--978},
     volume = {28},
     year = {2009}
    }
    

20. Timing Predictability of Cache Replacement Policies
    J. Reineke, D. Grund, C. Berg, and R. Wilhelm
    Real-Time Systems, 37(2), November 2007
    [doi] [pdf] [ppt slides] [bib]

    @article{Reineke07,
     title = {Timing Predictability of Cache Replacement Policies},
     author = {Reineke, Jan and Grund, Daniel and Berg, Christoph and Wilhelm, Reinhard},
     doi = {10.1007/s11241-007-9032-3},
     journal = {Real-Time Systems},
     month = {Nov},
     number = {2},
     pages = {99--122},
     slides = {http://rw4.cs.uni-saarland.de/~reineke/talks/predictabilityCacheReplacement.ppt},
     url = {http://rw4.cs.uni-saarland.de/~grund/papers/rts07-predictability.pdf},
     volume = {37},
     year = {2007}
    }
    

Conference and Workshop Papers

1. Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors (Best Paper Award Candidate )
   G. Mohr, M. Guarnieri, and J. Reineke
   DATE, March 2024
   [bib]

   @inproceedings{Mohr24,
    title = {Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors},
    author = {Mohr, Gideon and Guarnieri, Marco and Reineke, Jan},
    booktitle = {Design, Automation and Test in Europe Conference and Exhibition (DATE), 2024},
    month = {Mar},
    organization = {IEEE},
    year = {2024}
   }
   

2. FACILE: Fast, Accurate, and Interpretable Basic-Block Throughput Prediction
   A. Abel, S. Sharma, and J. Reineke
   IEEE International Symposium on Workload Characterization, IISWC 2023, Ghent, Belgium, October 1-3, 2023, 2023
   [doi] [bib]

   @inproceedings{Abel23,
    title = {{FACILE}: Fast, Accurate, and Interpretable Basic-Block Throughput Prediction},
    author = {Abel, Andreas and Sharma, Shrey and Reineke, Jan},
    booktitle = {{IEEE} International Symposium on Workload Characterization, {IISWC} 2023, Ghent, Belgium, October 1-3, 2023},
    publisher = {{IEEE}},
    year = {2023},
    doi = {10.1109/IISWC59245.2023.00023},
    url = {https://arxiv.org/pdf/2310.13212},
   }
   

3. Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis (Outstanding Paper Award )
   V. Touzeau and J. Reineke
   RTSS, 2023
   [bib]

   @inproceedings{Touzeau23,
    title = {Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis},
    author = {Touzeau, Valentin and Reineke, Jan},
    booktitle = {2023 {IEEE} Real-Time Systems Symposium, {RTSS} 2023, Taipei, Taiwan, December 5-8, 2023},
    year = {2023}
   }
   

4. Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts (Distinguished Paper Award at CCS 2023 and Intel Hardware Security Academic Award Finalist )
   Z. Wang, G. Mohr, K. Gleissenthall, J. Reineke, and M. Guarnieri
   CCS, 2023
   [bib]

   @inproceedings{wang2023specification,
    title = {Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts},
    author = {Wang, Zilong and Mohr, Gideon and Gleissenthall, Klaus von and Reineke, Jan and Guarnieri, Marco},
    booktitle = {Proceedings of the 30th ACM Conference on Computer and Communications Security},
    publisher = {ACM},
    series = {CCS 2023},
    year = {2023}
   }
   

5. uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
   A. Abel and J. Reineke
   ICS, 2022
   [bib]

   @inproceedings{Abel22,
    title = {{uiCA}: Accurate Throughput Prediction of Basic Blocks on Recent {Intel} Microarchitectures},
    author = {Abel, Andreas and Reineke, Jan},
    booktitle = {{ICS} '22: 2022 International Conference on Supercomputing, Virtual Event, USA, June 27-30, 2022},
     series = {ICS '22},
    editor = {Rauchwerger, Lawrence and Cameron, Kirk and Nikolopoulos, Dimitrios S. and Pnevmatikatos, Dionisios},
    pages = {1--12},
    publisher = {{ACM}},
    month = {June},
    year = {2022},
    url = {https://dl.acm.org/doi/pdf/10.1145/3524059.3532396}
   }
   

6. DiffTune Revisited: A Simple Baseline for Evaluating Learned llvm-mca Parameters
   Andreas Abel
   Machine Learning for Computer Architecture and Systems 2022, 2022
   [bib]

   @inproceedings{Abel22b,
    title={{DiffTune} Revisited: A Simple Baseline for Evaluating Learned llvm-mca Parameters},
    author={Andreas Abel},
    booktitle={Machine Learning for Computer Architecture and Systems 2022},
    month = {June},
    year={2022},
    url={https://openreview.net/forum?id=dw4evoj6AE}
   }
   

7. LLVMTA: An LLVM-Based WCET Analysis Tool
   S. Hahn, M. Jacobs, N. Hölscher, K. Chen, J. Chen, and J. Reineke
   WCET, 2022
   [doi] [bib]

   @inproceedings{hahn_et_al:OASIcs.WCET.2022.2,
    title = {{LLVMTA: An LLVM-Based WCET Analysis Tool}},
    address = {Dagstuhl, Germany},
    annote = {Keywords: WCET analysis, low-level analysis, LLVM},
    author = {Hahn, Sebastian and Jacobs, Michael and H{\"o}lscher, Nils and Chen, Kuan-Hsun and Chen, Jian-Jia and Reineke, Jan},
    booktitle = {20th International Workshop on Worst-Case Execution Time Analysis (WCET 2022)},
    doi = {10.4230/OASIcs.WCET.2022.2},
    editor = {Ballabriga, Cl\'{e}ment},
    isbn = {978-3-95977-244-0},
    issn = {2190-6807},
    pages = {2:1--2:17},
    publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
    series = {Open Access Series in Informatics (OASIcs)},
    url = {https://drops.dagstuhl.de/opus/volltexte/2022/16624},
    urn = {urn:nbn:de:0030-drops-166242},
    volume = {103},
    year = {2022}
   }
   

8. Warping Cache Simulation of Polyhedral Programs
   C. Morelli and J. Reineke
   PLDI, June 2022
   [doi] [bib]

   @inproceedings{Morelli22,
    title = {Warping Cache Simulation of Polyhedral Programs},
    address = {New York, NY, USA},
    author = {Morelli, Canberk and Reineke, Jan},
    booktitle = {PLDI},
    doi = {10.1145/3519939.3523714},
    isbn = {978-1-4503-9265-5/22/06},
    location = {San Diego, CA, USA},
    numpages = {16},
    publisher = {ACM},
    series = {PLDI '22},
    url = {http://doi.acm.org/10.1145/3519939.3523714},
    month = {Jun},
    year = {2022},
   }
   

9. On the Trade-offs between Generalization and Specialization in Real-Time Systems
   G. der Brüggen, A. Burns, J. Chen, R. Davis, and J. Reineke
   RTCSA, 2022
   [bib]

   @inproceedings{Brueggen22,
    title = {On the Trade-offs between Generalization and Specialization in Real-Time Systems},
    author = {der Br\"uggen, Georg von and Burns, Alan and Chen, Jian-Jia and Davis, Robert I. and Reineke, Jan},
    booktitle = {28th {IEEE} International Conference on Embedded and Real-Time Computing Systems and Applications, {RTCSA} 2022, Taipei, Taiwan, August 23-25, 2022},
    publisher = {{IEEE}},
    year = {2022}
   }
   

10. Hardware-Software Contracts for Secure Speculation (Best Paper Award )
    M. Guarnieri, B. Köpf, J. Reineke, and P. Vila
    S&P (Oakland), May 2021
    [bib]

    @inproceedings{Guarnieri21,
     title = {Hardware-Software Contracts for Secure Speculation},
     author = {Guarnieri, Marco and K{{\"o}}pf, Boris and Reineke, Jan and Vila, Pepe},
     booktitle = {2021 {IEEE} Symposium on Security and Privacy, {SP} 2021, Proceedings, San Francisco, California, {USA}},
     month = {May},
     url = {https://arxiv.org/abs/2006.03841},
     year = {2021}
    }
    

11. nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems
    A. Abel and J. Reineke
    ISPASS, August 2020
    [bib]

    @inproceedings{Abel20a,
     title = {nanoBench: {A} Low-Overhead Tool for Running Microbenchmarks on x86 Systems},
     author = {Abel, Andreas and Reineke, Jan},
     booktitle = {2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)},
     month = {Aug},
     year = {2020}
    }
    

12. SPECTECTOR: Principled Detection of Speculative Information Flows
    M. Guarnieri, B. Köpf, J. Morales, J. Reineke, and A. Sánchez
    S&P (Oakland), May 2020
    [pdf] [bib]

    @inproceedings{Guarnieri20,
     title = {{SPECTECTOR:} Principled Detection of Speculative Information Flows},
     author = {Guarnieri, Marco and K{{\"o}}pf, Boris and Morales, Jos{{\'e}} F. and Reineke, Jan and S{{\'a}}nchez, Andr{{\'e}}s},
     booktitle = {2020 {IEEE} Symposium on Security and Privacy, {SP} 2020, Proceedings, San Francisco, California, {USA}},
     month = {May},
     url = {https://spectector.github.io/papers/spectector.pdf},
     year = {2020}
    }
    

13. uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
    A. Abel and J. Reineke
    ASPLOS, 2019
    [doi] [bib]

    @inproceedings{Abel19a,
     title = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on {Intel} Microarchitectures},
     acmid = {3304062},
     address = {New York, NY, USA},
     author = {Abel, Andreas and Reineke, Jan},
     booktitle = {ASPLOS},
     doi = {10.1145/3297858.3304062},
     isbn = {978-1-4503-6240-5},
     location = {Providence, RI, USA},
     numpages = {14},
     pages = {673--686},
     publisher = {ACM},
     series = {ASPLOS '19},
     url = {http://doi.acm.org/10.1145/3297858.3304062},
     year = {2019}
    }
    

14. Multi-dimensional Vectorization in LLVM
    S. Moll, S. Sharma, M. Kurtenacker, and S. Hack
    Proceedings of the 5th Workshop on Programming Models for SIMD/Vector Processing, 2019
    [pdf] [bib]

    @inproceedings{moll2019multi,
      title={Multi-dimensional Vectorization in LLVM},
      author={Moll, Simon and Sharma, Shrey and Kurtenacker, Matthias and Hack, Sebastian},
      booktitle={Proceedings of the 5th Workshop on Programming Models for SIMD/Vector Processing},
      pages={3},
      year={2019},
      organization={ACM}
    }
    

15. Cache Persistence Analysis: Finally Exact (Best Paper Award )
    G. Stock, S. Hahn, and J. Reineke
    RTSS, December 2019
    [bib]

    @inproceedings{Stock19,
     title = {Cache Persistence Analysis: Finally Exact},
     author = {Stock, Gregory and Hahn, Sebastian and Reineke, Jan},
     booktitle = {RTSS},
     month = {Dec},
     year = {2019}
    }
    

16. Polyhedral expression propagation
    J. Doerfert, S. Sharma, and S. Hack
    Proceedings of the 27th International Conference on Compiler Construction, 2018
    [pdf] [bib]

    @inproceedings{doerfert2018polyhedral,
      title={Polyhedral expression propagation},
      author={Doerfert, Johannes and Sharma, Shrey and Hack, Sebastian},
      booktitle={Proceedings of the 27th International Conference on Compiler Construction},
      pages={25--36},
      year={2018},
      organization={ACM}
    }
    

17. Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core (Best Student Paper Award )
    S. Hahn and J. Reineke
    RTSS, December 2018
    [pdf] [pdf slides] [bib]

    @inproceedings{Hahn18,
     title = {Design and Analysis of {SIC}: A Provably Timing-Predictable Pipelined Processor Core},
     author = {Hahn, Sebastian and Reineke, Jan},
     booktitle = {RTSS},
     month = {Dec},
     year = {2018}
    }
    

18. Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis
    D. Shah, S. Hahn, and J. Reineke
    WCET, July 2018
    [bib]

    @inproceedings{Shah18,
     title = {Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis},
     author = {Shah, Darshit and Hahn, Sebastian and Reineke, Jan},
     booktitle = {15th International Workshop on Worst-Case Execution Time Analysis, {WCET} 2018, July 3, 2018, Barcelona, Spain},
     month = {Jul},
     year = {2018}
    }
    

19. Write-Back Caches in WCET Analysis (Outstanding Paper Award )
    T. Blaß , S. Hahn, and J. Reineke
    ECRTS, 2017
    [doi] [pdf] [pdf slides] [bib]

    @inproceedings{Blass17,
     title = {Write-Back Caches in {WCET} Analysis},
     author = {Bla{\ss }, Tobias and Hahn, Sebastian and Reineke, Jan},
     booktitle = {29th Euromicro Conference on Real-Time Systems, {ECRTS} 2017, June 27-30, 2017, Dubrovnik, Croatia},
     doi = {10.4230/LIPIcs.ECRTS.2017.26},
     pages = {26:1--26:22},
     url = {https://doi.org/10.4230/LIPIcs.ECRTS.2017.26},
     year = {2017}
    }
    

20. Security Analysis of Cache Replacement Policies (Nominated for "Best ETAPS Paper")
    P. Cañones, B. Köpf, and J. Reineke
    POST, 2017
    [doi] [pdf] [bib]

    @inproceedings{Canones17,
     title = {Security Analysis of Cache Replacement Policies},
     author = {Ca{{\~n}}ones, Pablo and K{{\"o}}pf, Boris and Reineke, Jan},
     booktitle = {Principles of Security and Trust - 6th International Conference, {POST} 2017, Held as Part of the European Joint Conferences on Theory and Practice of Software, {ETAPS} 2017, Uppsala, Sweden, April 22-29, 2017, Proceedings},
     doi = {10.1007/978-3-662-54455-6_9},
     pages = {189--209},
     url = {http://dx.doi.org/10.1007/978-3-662-54455-6_9},
     year = {2017}
    }
    

21. Memory Bank Partitioning for Fixed-Priority Tasks in a Multi-core System
    S. Cheng, J. Chen, J. Reineke, and T. Kuo
    RTSS, 2017
    [doi] [bib]

    @inproceedings{Cheng17,
     title = {Memory Bank Partitioning for Fixed-Priority Tasks in a Multi-core System},
     author = {Cheng, Sheng{-}Wei and Chen, Jian{-}Jia and Reineke, Jan and Kuo, Tei{-}Wei},
     booktitle = {2017 {IEEE} Real-Time Systems Symposium, {RTSS} 2017, Paris, France, December 5-8, 2017},
     doi = {10.1109/RTSS.2017.00027},
     pages = {209--219},
     url = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2017.00027},
     year = {2017}
    }
    

22. Abstract PRET Machines
    E. Lee, J. Reineke, and M. Zimmer
    RTSS, 2017
    [doi] [bib]

    @inproceedings{Lee17,
     title = {Abstract {PRET} Machines},
     author = {Lee, Edward A. and Reineke, Jan and Zimmer, Michael},
     booktitle = {2017 {IEEE} Real-Time Systems Symposium, {RTSS} 2017, Paris, France, December 5-8, 2017},
     doi = {10.1109/RTSS.2017.00041},
     pages = {1--11},
     url = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2017.00041},
     year = {2017}
    }
    

23. Ascertaining Uncertainty for Efficient Exact Cache Analysis
    V. Touzeau, C. Maiza, D. Monniaux, and J. Reineke
    CAV, July 2017
    [pdf] [bib]

    @inproceedings{Touzeau17,
     title = {Ascertaining Uncertainty for Efficient Exact Cache Analysis},
     author = {Touzeau, Valentin and Maiza, Claire and Monniaux, David and Reineke, Jan},
     booktitle = {CAV},
     month = {Jul},
     url = {http://embedded.cs.uni-saarland.de/publications/AscertainingUncertaintyForEfficientExactCacheAnalysisCAV2017.pdf},
     year = {2017}
    }
    

24. Gray-box Learning of Serial Compositions of Mealy Machines
    A. Abel and J. Reineke
    NFM, June 2016
    [doi] [pdf] [bib]

    @inproceedings{Abel16,
     title = {Gray-box Learning of Serial Compositions of {Mealy} Machines},
     author = {Abel, Andreas and Reineke, Jan},
     booktitle = {Nasa Formal Methods Symposium},
     doi = {10.1007/978-3-319-40648-0_21},
     month = {Jun},
     year = {2016}
    }
    

25. Analysis of Write-back Caches under Fixed-priority Preemptive and Non-preemptive Scheduling (Outstanding Paper Award )
    R. Davis, S. Altmeyer, and J. Reineke
    RTNS, October 2016
    [doi] [pdf] [bib]

    @inproceedings{Davis16,
     title = {Analysis of Write-back Caches under Fixed-priority Preemptive and Non-preemptive Scheduling},
     author = {Davis, Rob and Altmeyer, Sebastian and Reineke, Jan},
     booktitle = {Proceedings of the 24th International Conference on Real-Time Networks and Systems},
     doi = {10.1145/2997465.2997476},
     month = {Oct},
     year = {2016}
    }
    

26. Enabling Compositionality for Multicore Timing Analysis
    S. Hahn, M. Jacobs, and J. Reineke
    RTNS, October 2016
    [doi] [pdf] [bib]

    @inproceedings{Hahn16,
     title = {Enabling Compositionality for Multicore Timing Analysis},
     author = {Hahn, Sebastian and Jacobs, Michael and Reineke, Jan},
     booktitle = {Proceedings of the 24th International Conference on Real-Time Networks and Systems},
     doi = {10.1145/2997465.2997471},
     month = {Oct},
     url = {http://embedded.cs.uni-saarland.de/publications/EnablingCompositionalityRTNS2016.pdf},
     year = {2016}
    }
    

27. MIRROR: Symmetric Timing Analysis for Real-Time Tasks on Multicore Platforms with Shared Resources
    W. Huang, J. Chen, and J. Reineke
    DAC, June 2016
    [pdf] [bib]

    @inproceedings{Huang16,
     title = {{MIRROR}: Symmetric Timing Analysis for Real-Time Tasks on Multicore Platforms with Shared Resources},
     author = {Huang, Wen-Hung and Chen, Jian-Jia and Reineke, Jan},
     booktitle = {DAC},
     month = {Jun},
     url = {http://embedded.cs.uni-saarland.de/publications/MIRRORSymmetricTimingAnalysisDAC2016.pdf},
     year = {2016}
    }
    

28. Static Timing Analysis - What is Special?
    J. Reineke and R. Wilhelm
    Semantics, Logics, and Calculi - Essays Dedicated to Hanne Riis Nielson and Flemming Nielson on the Occasion of Their 60th Birthdays, 2016
    [doi] [bib]

    @inproceedings{Reineke16,
     title = {Static Timing Analysis - What is Special?},
     author = {Reineke, Jan and Wilhelm, Reinhard},
     booktitle = {Semantics, Logics, and Calculi - Essays Dedicated to Hanne Riis Nielson and Flemming Nielson on the Occasion of Their 60th Birthdays},
     doi = {10.1007/978-3-319-27810-0_4},
     pages = {74--87},
     url = {http://embedded.cs.uni-saarland.de/publications/TimingAnalysisWhatIsSpecial2016.pdf},
     year = {2016}
    }
    

29. MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy Machines
    A. Abel and J. Reineke
    ICCAD, 2015
    [doi] [pdf] [bib]

    @inproceedings{Abel15,
     title = {{MeMin}: {SAT-based} Exact Minimization of Incompletely Specified {Mealy} Machines},
     author = {Abel, Andreas and Reineke, Jan},
     booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
     doi = {10.1109/ICCAD.2015.7372555},
     pages = {94--101},
     url = {http://dx.doi.org/10.1109/ICCAD.2015.7372555},
     year = {2015}
    }
    

30. WCET and Mixed-Criticality: What does Confidence in WCET Estimations Depend Upon?
    S. Altmeyer, B. Lisper, C. Maiza, J. Reineke, and C. Rochange
    WCET, 2015
    [doi] [bib]

    @inproceedings{Altmeyer15,
     title = {{WCET} and Mixed-Criticality: What does Confidence in {WCET} Estimations Depend Upon?},
     author = {Altmeyer, Sebastian and Lisper, Bj{{\"o}}rn and Maiza, Claire and Reineke, Jan and Rochange, Christine},
     booktitle = {15th International Workshop on Worst-Case Execution Time Analysis, {WCET} 2015, July 7, 2015, Lund, Sweden},
     doi = {10.4230/OASIcs.WCET.2015.65},
     pages = {65--74},
     url = {http://dx.doi.org/10.4230/OASIcs.WCET.2015.65},
     year = {2015}
    }
    

31. A generic and compositional framework for multicore response time analysis (Outstanding Paper Award )
    S. Altmeyer, R. Davis, L. Indrusiak, C. Maiza, V. Nélis, and J. Reineke
    RTNS, 2015
    [doi] [pdf] [bib]

    @inproceedings{Altmeyer15b,
     title = {A generic and compositional framework for multicore response time analysis},
     author = {Altmeyer, Sebastian and Davis, Robert I. and Indrusiak, Leandro Soares and Maiza, Claire and N{{\'e}}lis, Vincent and Reineke, Jan},
     booktitle = {RTNS},
     doi = {10.1145/2834848.2834862},
     pages = {129--138},
     url = {http://doi.acm.org/10.1145/2834848.2834862},
     year = {2015}
    }
    

32. Analysis of Infinite-State Graph Transformation Systems by Cluster Abstraction
    P. Backes and J. Reineke
    VMCAI, 2015
    [doi] [pdf] [bib]

    @inproceedings{Backes15,
     title = {Analysis of Infinite-State Graph Transformation Systems by Cluster Abstraction},
     author = {Backes, Peter and Reineke, Jan},
     booktitle = {Verification, Model Checking, and Abstract Interpretation - 16th International Conference, {VMCAI} 2015, Mumbai, India, January 12-14, 2015. Proceedings},
     doi = {10.1007/978-3-662-46081-8_8},
     pages = {135--152},
     url = {http://dx.doi.org/10.1007/978-3-662-46081-8_8},
     year = {2015}
    }
    

33. ASTRA: A Tool for Abstract Interpretation of Graph Transformation Systems
    P. Backes and J. Reineke
    Model Checking Software - 22nd International Symposium, SPIN 2015, Stellenbosch, South Africa, August 24-26, 2015, Proceedings, 2015
    [doi] [bib]

    @inproceedings{Backes15b,
     title = {{ASTRA:} {A} Tool for Abstract Interpretation of Graph Transformation Systems},
     author = {Backes, Peter and Reineke, Jan},
     booktitle = {Model Checking Software - 22nd International Symposium, {SPIN} 2015, Stellenbosch, South Africa, August 24-26, 2015, Proceedings},
     doi = {10.1007/978-3-319-23404-5_2},
     pages = {13--19},
     url = {http://dx.doi.org/10.1007/978-3-319-23404-5_2},
     year = {2015}
    }
    

34. Toward Compact Abstractions for Processor Pipelines
    S. Hahn, J. Reineke, and R. Wilhelm
    Correct System Design - Symposium in Honor of Ernst-Rüdiger Olderog on the Occasion of His 60th Birthday, Oldenburg, Germany, September 8-9, 2015. Proceedings, 2015
    [doi] [pdf] [bib]

    @inproceedings{Hahn15b,
     title = {Toward Compact Abstractions for Processor Pipelines},
     author = {Hahn, Sebastian and Reineke, Jan and Wilhelm, Reinhard},
     booktitle = {Correct System Design - Symposium in Honor of Ernst-R{{\"u}}diger Olderog on the Occasion of His 60th Birthday, Oldenburg, Germany, September 8-9, 2015. Proceedings},
     doi = {10.1007/978-3-319-23506-6_14},
     editor = {Meyer, Roland and Platzer, André and Wehrheim, Heike},
     pages = {205--220},
     url = {http://dx.doi.org/10.1007/978-3-319-23506-6_14},
     year = {2015}
    }
    

35. On the Smoothness of Paging Algorithms
    J. Reineke and A. Salinger
    WAOA, 2015
    [doi] [pdf] [bib]

    @inproceedings{Reineke15,
     title = {On the Smoothness of Paging Algorithms},
     author = {Reineke, Jan and Salinger, Alejandro},
     booktitle = {Approximation and Online Algorithms - 13th International Workshop, {WAOA} 2015, Patras, Greece, September 17-18, 2015. Revised Selected Papers},
     doi = {10.1007/978-3-319-28684-6_15},
     pages = {170--182},
     url = {http://dx.doi.org/10.1007/978-3-319-28684-6_15},
     year = {2015}
    }
    

36. Reverse Engineering of Cache Replacement Policies in Intel Microprocessors and Their Evaluation (poster abstract)
    A. Abel and J. Reineke
    ISPASS, March 2014
    [pdf] [bib]

    @inproceedings{Abel14,
     title = {Reverse Engineering of Cache Replacement Policies in {Intel} Microprocessors and Their Evaluation},
     author = {Abel, Andreas and Reineke, Jan},
     booktitle = {2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)},
     month = {Mar},
     pages = {141-142},
     url = {http://embedded.cs.uni-saarland.de/publications/ISPASS14.pdf},
     year = {2014}
    }
    

37. A Compiler Optimization to Increase the Efficiency of WCET Analysis (Outstanding Paper Award )
    M. Maksoud and J. Reineke
    RTNS, 2014
    [doi] [pdf] [bib]

    @inproceedings{Maksoud14,
     title = {A Compiler Optimization to Increase the Efficiency of {WCET} Analysis},
     acmid = {2659825},
     address = {New York, NY, USA},
     articleno = {87},
     author = {Maksoud, Mohamed Abdel and Reineke, Jan},
     booktitle = {Proceedings of the 22Nd International Conference on Real-Time Networks and Systems},
     doi = {10.1145/2659787.2659825},
     isbn = {978-1-4503-2727-5},
     keyword = {WCET analysis efficiency, analyzability, predictability},
     location = {Versailles, France},
     numpages = {10},
     pages = {87:87--87:96},
     publisher = {ACM},
     series = {RTNS '14},
     url = {http://embedded.cs.uni-saarland.de/publications/ACompilerOptimizationToIncreaseWCETAnalysisEfficiencyRTNS2014.pdf},
     year = {2014}
    }
    

38. Architecture-Parametric Timing Analysis
    J. Reineke and J. Doerfert
    RTAS, April 2014
    [doi] [pdf] [pdf slides] [bib]

    @inproceedings{Reineke14,
     title = {Architecture-Parametric Timing Analysis},
     author = {Reineke, Jan and Doerfert, Johannes},
     booktitle = {20th {IEEE} Real-Time and Embedded Technology and Applications Symposium, {RTAS} 2014, Berlin, Germany, April 15-17, 2014},
     doi = {10.1109/RTAS.2014.6926002},
     month = {Apr},
     pages = {189--200},
     url = {http://embedded.cs.uni-saarland.de/publications/ArchitectureParametricTimingAnalysis-RTAS2014.pdf},
     year = {2014}
    }
    

39. Basic Problems in Multi-View Modeling
    J. Reineke and S. Tripakis
    TACAS, April 2014
    [doi] [pdf] [bib]

    @inproceedings{Reineke14a,
     title = {Basic Problems in Multi-View Modeling},
     author = {Reineke, Jan and Tripakis, Stavros},
     booktitle = {TACAS},
     doi = {10.1007/978-3-642-54862-8_15},
     month = {Apr},
     pages = {217-232},
     pdf = {http://embedded.cs.uni-saarland.de/publications/BasicProblemsInMultiViewModeling-TACAS2014.pdf},
     year = {2014}
    }
    

40. Selfish-LRU: Preemption-aware caching for predictability and performance
    J. Reineke, S. Altmeyer, D. Grund, S. Hahn, and C. Maiza
    RTAS, April 2014
    [doi] [pdf] [pdf slides] [bib]

    @inproceedings{Reineke14b,
     title = {Selfish-LRU: Preemption-aware caching for predictability and performance},
     author = {Reineke, Jan and Altmeyer, Sebastian and Grund, Daniel and Hahn, Sebastian and Maiza, Claire},
     booktitle = {20th {IEEE} Real-Time and Embedded Technology and Applications Symposium, {RTAS} 2014, Berlin, Germany, April 15-17, 2014},
     doi = {10.1109/RTAS.2014.6925997},
     month = {Apr},
     pages = {135--144},
     url = {http://embedded.cs.uni-saarland.de/publications/SelfishLRU-RTAS-2014.pdf},
     year = {2014}
    }
    

41. Impact of Resource Sharing on Performance and Performance Prediciton: A Survey (invited paper, extended abstract)
    J. Reineke and R. Wilhelm
    DATE, March 2014
    [bib]

    @inproceedings{Reineke14d,
     title = {Impact of Resource Sharing on Performance and Performance Prediciton: A Survey},
     author = {Reineke, Jan and Wilhelm, Reinhard},
     booktitle = {Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014},
     month = {Mar},
     organization = {IEEE},
     pages = {1--2},
     year = {2014}
    }
    

42. Measurement-based Modeling of the Cache Replacement Policy
    A. Abel and J. Reineke
    RTAS, April 2013
    [pdf] [pdf slides] [ppt slides] [bib]

    @inproceedings{Abel13,
     title = {Measurement-based Modeling of the Cache Replacement Policy},
     author = {Abel, Andreas and Reineke, Jan},
     booktitle = {19th {IEEE} Real-Time and Embedded Technology and Applications Symposium, {RTAS} 2013, Philadelphia, PA, USA, April 9-11, 2013},
     month = {Apr},
     pages = {65--74},
     slides = {http://embedded.cs.uni-saarland.de/presentations/LearningCacheModels.pptx},
     slidespdf = {http://embedded.cs.uni-saarland.de/presentations/LearningCacheModels.pdf},
     url = {http://embedded.cs.uni-saarland.de/publications/CacheModelingRTAS2013.pdf},
     year = {2013}
    }
    

43. Impact of Resource Sharing on Performance and Performance Prediction: A Survey
    A. Abel, F. Benz, J. Doerfert, B. Dörr, S. Hahn, F. Haupenthal, M. Jacobs, A. Moin, J. Reineke, B. Schommer, and R. Wilhelm
    CONCUR, August 2013
    [doi] [pdf] [bib]

    @inproceedings{Abel13b,
     title = {Impact of Resource Sharing on Performance and Performance Prediction: {A} Survey},
     author = {Abel, Andreas and Benz, Florian and Doerfert, Johannes and D\"orr, Barbara and Hahn, Sebastian and Haupenthal, Florian and Jacobs, Michael and Moin, Amir H. and Reineke, Jan and Schommer, Bernhard and Wilhelm, Reinhard},
     booktitle = {{CONCUR} 2013 - Concurrency Theory - 24th International Conference, {CONCUR} 2013, Buenos Aires, Argentina, August 27-30, 2013. Proceedings},
     doi = {10.1007/978-3-642-40184-8_3},
     month = {Aug},
     pages = {25--43},
     url = {http://embedded.cs.uni-saarland.de/publications/ResourceSharingSurvey.pdf},
     year = {2013}
    }
    

44. Precise timing analysis for direct-mapped caches
    S. Andalam, A. Girault, R. Sinha, P. Roop, and J. Reineke
    DAC, 2013
    [doi] [bib]

    @inproceedings{Andalam13,
     title = {Precise timing analysis for direct-mapped caches},
     author = {Andalam, Sidharta and Girault, Alain and Sinha, Roopak and Roop, Partha S. and Reineke, Jan},
     bibsource = {DBLP, http://dblp.uni-trier.de},
     booktitle = {DAC},
     doi = {10.1145/2463209.2488917},
     pages = {148},
     year = {2013}
    }
    

45. CacheAudit: A Tool for the Static Analysis of Cache Side Channels
    G. Doychev, D. Feld, B. Köpf, L. Mauborgne, and J. Reineke
    USENIX Security, August 2013
    [pdf] [bib]

    @inproceedings{Doychev13,
     title = {{CacheAudit}: {A} Tool for the Static Analysis of Cache Side Channels},
     author = {Doychev, Goran and Feld, Dominik and K\"opf, Boris and Mauborgne, Laurent and Reineke, Jan},
     booktitle = {Proceedings of the 22th {USENIX} Security Symposium, Washington, DC, USA, August 14-16, 2013},
     month = {Aug},
     pages = {431--446},
     url = {http://embedded.cs.uni-saarland.de/publications/CacheAuditUSENIXSecurity13.pdf},
     year = {2013}
    }
    

46. Towards Compositionality in Execution Time Analysis -- Definition and Challenges
    S. Hahn, J. Reineke, and R. Wilhelm
    CRTS, December 2013
    [pdf] [bib]

    @inproceedings{Hahn13,
     title = {Towards Compositionality in Execution Time Analysis -- Definition and Challenges},
     author = {Hahn, Sebastian and Reineke, Jan and Wilhelm, Reinhard},
     booktitle = {6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems (CRTS)},
     month = {Dec},
     url = {http://embedded.cs.uni-saarland.de/publications/TowardsCompositionality.pdf},
     year = {2013}
    }
    

47. Automatic Cache Modeling by Measurements
    A. Abel and J. Reineke
    JRWRTC, November 2012
    [pdf] [bib]

    @inproceedings{Abel12,
     title = {Automatic Cache Modeling by Measurements},
     author = {Abel, Andreas and Reineke, Jan},
     booktitle = {6th Junior Researcher Workshop on Real-Time Computing (in conjunction with RTNS)},
     month = {Nov},
     url = {http://embedded.cs.uni-saarland.de/publications/CacheModelingJRWRTC.pdf},
     year = {2012}
    }
    

48. A PRET Microarchitecture Implementation with Repeatable Timing and Competitive Performance
    I. Liu, J. Reineke, D. Broman, M. Zimmer, and E. Lee
    ICCD, September 2012
    [pdf] [bib]

    @inproceedings{Liu12,
     title = {A PRET Microarchitecture Implementation with Repeatable Timing and Competitive Performance},
     author = {Liu, Isaac and Reineke, Jan and Broman, David and Zimmer, Michael and Lee, Edward A.},
     booktitle = {ICCD},
     month = {Sep},
     year = {2012}
    }
    

49. An Empirical Evaluation of the Influence of the Load-Store Unit on WCET Analysis
    M. Maksoud and J. Reineke
    WCET, 2012
    [doi] [pdf] [bib]

    @inproceedings{AbdelMaksoud12,
     title = {An Empirical Evaluation of the Influence of the Load-Store Unit on {WCET} Analysis},
     address = {Dagstuhl, Germany},
     author = {Maksoud, Mohamed Abdel and Reineke, Jan},
     booktitle = {12th International Workshop on Worst-Case Execution Time Analysis},
     doi = {10.4230/OASIcs.WCET.2012.13},
     editor = {Vardanega, Tullio},
     isbn = {978-3-939897-41-5},
     issn = {2190-6807},
     pages = {13--24},
     publisher = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
     series = {OpenAccess Series in Informatics (OASIcs)},
     url = {http://drops.dagstuhl.de/opus/volltexte/2012/3553},
     urn = {urn:nbn:de:0030-drops-35536},
     volume = {23},
     year = {2012}
    }
    

50. Embedded Systems: Many Cores - Many Problems
    R. Wilhelm and J. Reineke
    SIES, June 2012
    [doi] [pdf] [bib]

    @inproceedings{Wilhelm12,
     title = {Embedded Systems: Many Cores - Many Problems},
     author = {Wilhelm, Reinhard and Reineke, Jan},
     booktitle = {SIES},
     doi = {10.1109/SIES.2012.6356583},
     month = {Jun},
     pages = {176--180},
     year = {2012}
    }
    

51. Temporal Isolation on Multiprocessing Architectures
    D. Bui, E. Lee, I. Liu, H. Patel, and J. Reineke
    DAC, 2011
    [doi] [pdf] [bib]

    @inproceedings{Bui11,
     title = {Temporal Isolation on Multiprocessing Architectures},
     author = {Bui, Dai Nguyen and Lee, Edward A. and Liu, Isaac and Patel, Hiren D. and Reineke, Jan},
     booktitle = {DAC '11: Design Automation Conference},
     doi = {10.1145/2024724.2024787},
     url = {http://chess.eecs.berkeley.edu/pubs/839.html},
     year = {2011}
    }
    

52. A Template for Predictability Definitions with Supporting Evidence
    D. Grund, J. Reineke, and R. Wilhelm
    Bringing Theory to Practice: Predictability and Performance in Embedded Systems, 2011
    [doi] [pdf slides] [bib]

    @inproceedings{Grund11,
     title = {A Template for Predictability Definitions with Supporting Evidence},
     address = {Dagstuhl, Germany},
     author = {Grund, Daniel and Reineke, Jan and Wilhelm, Reinhard},
     booktitle = {Bringing Theory to Practice: Predictability and Performance in Embedded Systems},
     doi = {10.4230/OASIcs.PPES.2011.22},
     editor = {Lucas, Philipp and Thiele, Lothar and Triquet, Benoit and Ungerer, Theo and Wilhelm, Reinhard},
     isbn = {978-3-939897-28-6},
     issn = {2190-6807},
     pages = {22--31},
     publisher = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
     series = {OpenAccess Series in Informatics (OASIcs)},
     slides = {http://rw4.cs.uni-saarland.de/~grund/talks/ppes11-predictability_template.pdf},
     url = {http://drops.dagstuhl.de/opus/volltexte/2011/3078},
     urn = {urn:nbn:de:0030-drops-30785},
     volume = {18},
     year = {2011}
    }
    

53. CAMA: A Predictable Cache-Aware Memory Allocator
    J. Jörg Herter, Peter Backes, Florian Haupenthal
    ECRTS, July 2011
    [doi] [pdf] [bib]

    @inproceedings{Herter11,
     title = {{CAMA:} {A} Predictable Cache-Aware Memory Allocator},
     author = {J{\"o}rg Herter, Peter Backes, Florian Haupenthal, Jan Reineke},
     booktitle = {23rd Euromicro Conference on Real-Time Systems, {ECRTS} 2011, Porto, Portugal, 5-8 July, 2011},
     doi = {10.1109/ECRTS.2011.11},
     month = {Jul},
     pages = {23--32},
     url = {http://dx.doi.org/10.1109/ECRTS.2011.11},
     year = {2011}
    }
    

54. PRET DRAM Controller: Bank Privatization for Predictability and Temporal Isolation
    J. Reineke, I. Liu, H. Patel, S. Kim, and E. Lee
    CODES+ISSS, 2011
    [doi] [pdf] [pdf slides] [bib]

    @inproceedings{Reineke11,
     title = {PRET DRAM Controller: Bank Privatization for Predictability and Temporal Isolation},
     author = {Reineke, Jan and Liu, Isaac and Patel, Hiren D. and Kim, Sungjun and Lee, Edward A.},
     booktitle = {CODES+ISSS},
     doi = {10.1145/2039370.2039388},
     url = {http://chess.eecs.berkeley.edu/pubs/851.html},
     year = {2011}
    }
    

55. Designing next-generation real-time streaming systems
    S. Stuijk, T. Basten, B. Akesson, M. Geilen, O. Moreira, and J. Reineke
    CODES+ISSS, 2011
    [doi] [bib]

    @inproceedings{Stuijk11,
     title = {Designing next-generation real-time streaming systems},
     author = {Stuijk, Sander and Basten, Twan and Akesson, Benny and Geilen, Marc and Moreira, Orlando and Reineke, Jan},
     booktitle = {CODES+ISSS},
     doi = {10.1145/2039370.2039428},
     year = {2011}
    }
    

56. Resilience Analysis: Tightening the CRPD Bound for Set-Associative Caches
    S. Altmeyer, C. Maiza, and J. Reineke
    LCTES, April 2010
    [doi] [pdf] [pdf slides] [bib]

    @inproceedings{Altmeyer10,
     title = {Resilience Analysis: Tightening the CRPD Bound for Set-Associative Caches},
     address = {New York, NY, USA},
     author = {Altmeyer, Sebastian and Maiza, Claire and Reineke, Jan},
     booktitle = {LCTES '10: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems},
     doi = {10.1145/1755888.1755911},
     isbn = {978-1-60558-953-4},
     location = {Stockholm, Sweden},
     month = {Apr},
     pages = {153--162},
     publisher = {ACM},
     slides = {http://rw4.cs.uni-saarland.de/~reineke/talks/resilienceAnalysisAVACS09.pdf},
     url = {http://embedded.cs.uni-saarland.de/publications/ResilienceLCTES10.pdf},
     year = {2010}
    }
    

57. Abstract Topology Analysis of the Join Phase of the Merge Protocol
    P. Backes and J. Reineke
    Transformation Tool Contest 2010, 2010
    [pdf] [pdf slides] [bib]

    @inproceedings{Backes10,
     title = {Abstract Topology Analysis of the Join Phase of the Merge Protocol},
     address = {Enschede},
     author = {Backes, Peter and Reineke, Jan},
     booktitle = {Transformation Tool Contest 2010},
     pages = {127--133},
     publisher = {University of Twente},
     series = {{CTIT} Workshop Proceedings},
     slides = {http://rw4.cs.uni-sb.de/~rtc/ttc10bs.pdf},
     url = {http://rw4.cs.uni-sb.de/~rtc/ttc2010b.pdf},
     volume = {WP10-03},
     year = {2010}
    }
    

58. A Graph Transformation Case Study for the Topology Analysis of Dynamic Communication System
    P. Backes and J. Reineke
    Transformation Tool Contest 2010, 2010
    [pdf] [pdf slides] [bib]

    @inproceedings{Backes10a,
     title = {A Graph Transformation Case Study for the Topology Analysis of Dynamic Communication System},
     address = {Enschede},
     author = {Backes, Peter and Reineke, Jan},
     booktitle = {Transformation Tool Contest 2010},
     pages = {107--118},
     publisher = {University of Twente},
     series = {{CTIT} Workshop Proceedings},
     slides = {http://rw4.cs.uni-sb.de/~rtc/ttc10s.pdf},
     url = {http://rw4.cs.uni-sb.de/~rtc/ttc2010.pdf},
     volume = {WP10-03},
     year = {2010}
    }
    

59. Predictability Considerations in the Design of Multi-Core Embedded Systems
    C. Cullmann, C. Ferdinand, G. Gebhard, D. Grund, C. Maiza, J. Reineke, B. Triquet, and R. Wilhelm
    ERTSS, May 2010
    [pdf] [bib]

    @inproceedings{Cullmann10,
     title = {Predictability Considerations in the Design of Multi-Core Embedded Systems},
     author = {Cullmann, Christoph and Ferdinand, Christian and Gebhard, Gernot and Grund, Daniel and Maiza, Claire and Reineke, Jan and Triquet, Beno\^\i t and Wilhelm, Reinhard},
     booktitle = {Proceedings of Embedded Real Time Software and Systems},
     month = {May},
     url = {http://www.erts2010.org/Site/0ANDGY78/Fichier/PAPIERS%20ERTS%202010/ERTS2010_0049_final.pdf},
     year = {2010}
    }
    

60. Precise and Efficient FIFO-Replacement Analysis Based on Static Phase Detection
    D. Grund and J. Reineke
    ECRTS, July 2010
    [doi] [pdf] [pdf slides] [bib]

    @inproceedings{Grund10,
     title = {Precise and Efficient {FIFO}-Replacement Analysis Based on Static Phase Detection},
     author = {Grund, Daniel and Reineke, Jan},
     booktitle = {Proceedings of the 22nd Euromicro Conference on Real-Time Systems (ECRTS '10)},
     doi = {10.1109/ECRTS.2010.8},
     isbn = {978-1-4244-7546-9},
     issn = {1068-3070},
     location = {Brussels, Belgium},
     month = {Jul},
     pages = {155--164},
     slides = {http://rw4.cs.uni-saarland.de/~grund/talks/ecrts10-fifo.pdf},
     url = {http://rw4.cs.uni-saarland.de/~grund/papers/ecrts10-fifo_phases.pdf},
     year = {2010}
    }
    

61. Toward Precise PLRU Cache Analyis
    D. Grund and J. Reineke
    WCET, July 2010
    [pdf] [pdf slides] [bib]

    @inproceedings{Grund10a,
     title = {Toward Precise {PLRU} Cache Analyis},
     author = {Grund, Daniel and Reineke, Jan},
     booktitle = {Proceedings of 10th International Workshop on Worst-Case Execution Time ({WCET}) Analysis},
     editor = {Lisper, Bj\"orn},
     month = {Jul},
     pages = {28--39},
     publisher = {Austrian Computer Society},
     slides = {http://rw4.cs.uni-saarland.de/~grund/talks/wcet10-plru.pdf},
     url = {http://rw4.cs.uni-saarland.de/~grund/papers/wcet10-plru.pdf},
     year = {2010}
    }
    

62. A PRET Architecture Supporting Concurrent Programs with Composable Timing Properties
    I. Liu, J. Reineke, and E. Lee
    44th Asilomar Conference on Signals, Systems, and Computers, November 2010
    [pdf] [bib]

    @inproceedings{Liu10,
     title = {A PRET Architecture Supporting Concurrent Programs with Composable Timing Properties},
     author = {Liu, Isaac and Reineke, Jan and Lee, Edward A.},
     booktitle = {44th Asilomar Conference on Signals, Systems, and Computers},
     month = {Nov},
     url = {http://chess.eecs.berkeley.edu/pubs/803.html},
     year = {2010}
    }
    

63. Static Timing Analysis for Hard Real-Time Systems
    R. Wilhelm, S. Altmeyer, C. Burguière, D. Grund, J. Herter, J. Reineke, B. Wachter, and S. Wilhelm
    VMCAI, 2010
    [doi] [pdf] [bib]

    @inproceedings{Wilhelm10,
     title = {Static Timing Analysis for Hard Real-Time Systems},
     author = {Wilhelm, Reinhard and Altmeyer, Sebastian and Burgui\`ere, Claire and Grund, Daniel and Herter, J\"org and Reineke, Jan and Wachter, Bj\"orn and Wilhelm, Stephan},
     booktitle = {VMCAI},
     doi = {10.1007/978-3-642-11319-2_3},
     pages = {3--22},
     publisher = {Springer Verlag},
     year = {2010}
    }
    

64. Cache-Related Preemption Delay Computation for Set-Associative Caches---Pitfalls and Solutions
    C. Burguière, J. Reineke, and S. Altmeyer
    WCET, June 2009
    [pdf] [pdf slides] [bib]

    @inproceedings{Burguiere09,
     title = {Cache-Related Preemption Delay Computation for Set-Associative Caches---Pitfalls and Solutions},
     author = {Burgui\`ere, Claire and Reineke, Jan and Altmeyer, Sebastian},
     booktitle = {Proceedings of 9th International Workshop on Worst-Case Execution Time ({WCET}) Analysis},
     month = {Jun},
     slides = {http://rw4.cs.uni-saarland.de/~reineke/talks/CRPDPitfallsWCET09.pdf},
     url = {http://drops.dagstuhl.de/opus/volltexte/2009/2285/pdf/Burguiere.2285.pdf},
     year = {2009}
    }
    

65. Polynomial Precise Interval Analysis Revisited
    T. Gawlitza, J. Leroux, J. Reineke, H. Seidl, G. Sutre, and R. Wilhelm
    Efficient Algorithms, 2009
    [doi] [pdf] [bib]

    @inproceedings{Gawlitza09,
     title = {Polynomial Precise Interval Analysis Revisited},
     author = {Gawlitza, Thomas and Leroux, J\'er\^ome and Reineke, Jan and Seidl, Helmut and Sutre, Gr\'egoire and Wilhelm, Reinhard},
     booktitle = {Efficient Algorithms},
     doi = {10.1007/978-3-642-03456-5_28},
     pages = {422--437},
     url = {http://hal.archives-ouvertes.fr/docs/00/41/47/50/PDF/2009.Gawlitza.EA.pdf},
     year = {2009}
    }
    

66. Abstract Interpretation of FIFO Replacement
    D. Grund and J. Reineke
    SAS, August 2009
    [doi] [pdf] [pdf slides] [bib]

    @inproceedings{Grund09,
     title = {Abstract Interpretation of {FIFO} Replacement},
     author = {Grund, Daniel and Reineke, Jan},
     booktitle = {Static Analysis, 16th International Symposium, SAS 2009},
     doi = {10.1007/978-3-642-03237-0},
     editor = {Palsberg, Jens and Su, Zhendong},
     month = {Aug},
     pages = {120--136},
     publisher = {Springer-Verlag},
     series = {LNCS},
     slides = {http://rw4.cs.uni-saarland.de/~grund/talks/sas09-fifo.pdf},
     url = {http://rw4.cs.uni-saarland.de/~grund/papers/sas09-AI_FIFO.pdf},
     volume = {5673},
     year = {2009}
    }
    

67. Branch Target Buffers: WCET Analysis and Timing Predictability
    D. Grund, J. Reineke, and G. Gebhard
    RTCSA, August 2009
    [doi] [pdf] [pdf slides] [bib]

    @inproceedings{Grund09a,
     title = {Branch Target Buffers: {WCET} Analysis and Timing Predictability},
     author = {Grund, Daniel and Reineke, Jan and Gebhard, Gernot},
     booktitle = {15th International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009},
     doi = {10.1109/RTCSA.2009.8},
     month = {Aug},
     slides = {http://rw4.cs.uni-saarland.de/~grund/talks/rtcsa09-btb.pdf},
     url = {http://rw4.cs.uni-saarland.de/~grund/papers/rtcsa09-BTBs.pdf},
     year = {2009}
    }
    

68. Making Dynamic Memory Allocation Static To Support WCET Analyses
    J. Herter and J. Reineke
    WCET, June 2009
    [pdf] [pdf slides] [bib]

    @inproceedings{Herter09,
     title = {Making Dynamic Memory Allocation Static To Support {WCET} Analyses},
     author = {Herter, J\"org and Reineke, Jan},
     booktitle = {Proceedings of 9th International Workshop on Worst-Case Execution Time ({WCET}) Analysis},
     month = {Jun},
     slides = {http://rw4.cs.uni-saarland.de/~reineke/talks/makingDynamicAllocationStaticWCET09.pdf},
     url = {http://drops.dagstuhl.de/opus/volltexte/2009/2284/pdf/Herter.2284.pdf},
     year = {2009}
    }
    

69. Sound and Efficient WCET Analysis in the Presence of Timing Anomalies
    J. Reineke and R. Sen
    WCET, June 2009
    [pdf] [pdf slides] [bib]

    @inproceedings{Reineke09,
     title = {Sound and Efficient {WCET} Analysis in the Presence of Timing Anomalies},
     author = {Reineke, Jan and Sen, Rathijit},
     booktitle = {Proceedings of 9th International Workshop on Worst-Case Execution Time ({WCET}) Analysis},
     month = {Jun},
     slides = {http://rw4.cs.uni-saarland.de/~reineke/talks/preciseAndEfficientTimingAnomaliesWCET09.pdf},
     url = {http://rw4.cs.uni-saarland.de/~reineke/publications/TimingAnomaliesWCET09.pdf},
     year = {2009}
    }
    

70. Designing Predictable Multicore Architectures for Avionics and Automotive Systems
    R. Wilhelm, C. Ferdinand, C. Cullmann, D. Grund, J. Reineke, and B. Triquet
    Workshop on Reconciling Performance with Predictability (RePP), October 2009
    [pdf] [bib]

    @inproceedings{Wilhelm09b,
     title = {Designing Predictable Multicore Architectures for Avionics and Automotive Systems},
     author = {Wilhelm, Reinhard and Ferdinand, Christian and Cullmann, Christoph and Grund, Daniel and Reineke, Jan and Triquet, Beno\^\i t},
     booktitle = {Workshop on Reconciling Performance with Predictability ({RePP})},
     month = {Oct},
     url = {http://www.tik.ee.ethz.ch/~jchen/RePP/papers/2-3.pdf},
     year = {2009}
    }
    

71. Estimating the Performance of Cache Replacement Policies
    D. Grund and J. Reineke
    MEMOCODE, June 2008
    [doi] [pdf] [pdf slides] [bib]

    @inproceedings{Grund08,
     title = {Estimating the Performance of Cache Replacement Policies},
     author = {Grund, Daniel and Reineke, Jan},
     booktitle = {MEMOCODE '08: Proceedings of the 6th IEEE/ACM International Conference on Formal Methods and Models for Codesign},
     doi = {10.1109/MEMCOD.2008.4547695},
     month = {Jun},
     pages = {101--111},
     slides = {http://rw4.cs.uni-saarland.de/~grund/talks/memocode08-policy_performance.pdf},
     url = {http://rw4.cs.uni-saarland.de/~grund/papers/memocode08-policy_performance.pdf},
     year = {2008}
    }
    

72. CAMA: Cache-Aware Memory Allocation for WCET Analysis
    J. Herter, J. Reineke, and R. Wilhelm
    ECRTS, July 2008
    [pdf] [pdf slides] [bib]

    @inproceedings{Herter08a,
     title = {{CAMA}: Cache-Aware Memory Allocation for {WCET} Analysis},
     author = {Herter, J\"org and Reineke, Jan and Wilhelm, Reinhard},
     booktitle = {Proceedings Work-In-Progress Session of the 20th Euromicro Conference on Real-Time Systems},
     editor = {Caccamo, Marco},
     month = {Jul},
     pages = {24--27},
     slides = {http://rw4.cs.uni-saarland.de/~jherter/talks/ecrtswip08.pdf},
     url = {http://rw4.cs.uni-saarland.de/~jherter/papers/camaecrts08.pdf},
     year = {2008}
    }
    

73. Relative Competitiveness of Cache Replacement Policies
    J. Reineke and D. Grund
    SIGMETRICS, June 2008
    [doi] [pdf] [bib]

    @inproceedings{Reineke08b,
     title = {Relative Competitiveness of Cache Replacement Policies},
     address = {New York, NY, USA},
     author = {Reineke, Jan and Grund, Daniel},
     booktitle = {SIGMETRICS '08: Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems},
     doi = {10.1145/1375457.1375506},
     isbn = {978-1-60558-005-0},
     location = {Annapolis, MD, USA},
     month = {Jun},
     pages = {431--432},
     publisher = {ACM},
     url = {http://rw4.cs.uni-saarland.de/~grund/papers/sigmetrics08-rel_comp.pdf},
     year = {2008}
    }
    

74. Relative Competitive Analysis of Cache Replacement Policies
    J. Reineke and D. Grund
    LCTES, June 2008
    [doi] [pdf] [pdf slides] [bib]

    @inproceedings{Reineke08c,
     title = {Relative Competitive Analysis of Cache Replacement Policies},
     address = {New York, NY, USA},
     author = {Reineke, Jan and Grund, Daniel},
     booktitle = {LCTES '08: Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems},
     doi = {10.1145/1375657.1375665},
     isbn = {978-1-60558-104-0},
     location = {Tucson, AZ, USA},
     month = {Jun},
     pages = {51--60},
     publisher = {ACM},
     slides = {http://rw4.cs.uni-saarland.de/~reineke/talks/relativeCompetitiveAnalysisLCTES08.pdf},
     url = {http://rw4.cs.uni-saarland.de/~grund/papers/lctes08-rel_comp.pdf},
     year = {2008}
    }
    

75. Shape Analysis of Sets
    J. Reineke
    Workshop Trustworthy Software 2006, 2006
    [pdf] [pdf slides] [bib]

    @inproceedings{Reineke06,
     title = {Shape Analysis of Sets},
     address = {Dagstuhl, Germany},
     author = {Reineke, Jan},
     booktitle = {Workshop Trustworthy Software 2006},
     editor = {Autexier, Serge and Merz, Stephan and der Torre, Leon van and Wilhelm, Reinhard and Wolper, Pierre},
     publisher = {Internationales Begegnungs- und Forschungszentrum fuer Informatik
    (IBFI), Schloss Dagstuhl, Germany},
     slides = {http://rw4.cs.uni-saarland.de/~reineke/talks/shapeAnalysisOfSets.pdf},
     url = {http://drops.dagstuhl.de/opus/volltexte/2006/698/pdf/06000.ReinekeJan.Paper.698.pdf},
     year = {2006}
    }
    

76. A Definition and Classification of Timing Anomalies
    J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian, J. Eisinger, and B. Becker
    WCET, July 2006
    [pdf] [ppt slides] [bib]

    @inproceedings{Reineke06b,
     title = {A Definition and Classification of Timing Anomalies},
     author = {Reineke, Jan and Wachter, Bj\"orn and Thesing, Stephan and Wilhelm, Reinhard and Polian, Ilia and Eisinger, Jochen and Becker, Bernd},
     booktitle = {Proceedings of 6th International Workshop on Worst-Case Execution Time ({WCET}) Analysis},
     month = {Jul},
     slides = {http://rw4.cs.uni-saarland.de/~reineke/talks/timingAnomaliesWCET06.ppt},
     url = {http://rw4.cs.uni-saarland.de/~reineke/publications/TimingAnomaliesWCET06.pdf},
     year = {2006}
    }
    

Technical Reports

1. Analysis of Write-back Caches under Fixed-priority Preemptive and Non-preemptive Scheduling
   R. Davis, S. Altmeyer, and J. Reineke
   Technical Report, Dept. Computer Science, University of York, 2016
   [pdf] [bib]

   @techreport{Davis16b,
    title = {Analysis of Write-back Caches under Fixed-priority Preemptive and Non-preemptive Scheduling},
    author = {Davis, Robert I. and Altmeyer, Sebastian and Reineke, Jan},
    institution = {Dept. Computer Science, University of York},
    url = {https://www.cs.york.ac.uk/ftpdir/reports/2016/YCS/502/YCS-2016-502.pdf},
    year = {2016}
   }
   

2. A generic and compositional framework for multicore response time analysis
   S. Altmeyer, R. Davis, L. Indrusiak, C. Maiza, V. Nélis, and J. Reineke
   Technical Report, Dept. Computer Science, University of York, 2015
   [pdf] [bib]

   @techreport{Altmeyer15r,
    title = {A generic and compositional framework for multicore response time analysis},
    author = {Altmeyer, Sebastian and Davis, Robert I. and Indrusiak, Leandro Soares and Maiza, Claire and N{{\'e}}lis, Vincent and Reineke, Jan},
    institution = {Dept. Computer Science, University of York},
    url = {https://www.cs.york.ac.uk/ftpdir/reports/2015/YCS/499/YCS-2015-499.pdf},
    year = {2015}
   }
   

3. Basic Problems in Multi-View Modeling
   J. Reineke and S. Tripakis
   Technical Report, EECS Department, University of California, Berkeley, January 2014
   [pdf] [bib]

   @techreport{Reineke14c,
    title = {Basic Problems in Multi-View Modeling},
    abstract = {Modeling all aspects of a complex system within a single model is a difficult, if not impossible, task. Multi-view modeling is a methodology where different aspects of the system are captured by different models, or views. A key question then is consistency: if different views of a system have some degree of overlap, how can we guarantee that they are consistent, i.e., that they do not contradict each other? In this paper we formulate this and other basic problems in multi-view modeling within an abstract formal framework. We then instantiate this framework in a discrete, finite-state system setting, and study how some key verification and synthesis problems can be solved in that setting.},
    author = {Reineke, Jan and Tripakis, Stavros},
    institution = {EECS Department, University of California, Berkeley},
    month = {Jan},
    number = {UCB/EECS-2014-4},
    url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-4.html},
    year = {2014}
   }
   

4. Precise Modelling of Instruction Cache Behaviour
   S. Andalam, R. Sinha, P. Roop, A. Girault, and J. Reineke
   Technical Report, INRIA, January 2013
   [pdf] [bib]

   @techreport{Andalam13b,
    title = {Precise Modelling of Instruction Cache Behaviour},
    abstract = {{Safety critical real-time applications in aviation, automotive and industrial automation have to guarantee not only the functionality, but also the timeliness of the results. Here, a deadline is associated with the software tasks, and a failure to complete prior to this deadline could lead to a catastrophic consequences. Hence, for the correctness of real-time systems, it is essential to be able to compute the worst case execution time (WCET) of the tasks in order to guarantee their deadlines. However, the problem of WCET analysing is difficult, because of processors use cache-based memory systems that vary memory access time significantly. Any pessimistic estimation of the number of cache hits/misses will result in loose precision of the WCET analyses, which could lead to over use of hardware resources. In this paper, we present a new approach for statically analysing the behaviour of instructions on a direct mapped cache. The proposed approach combines binary representation and a new abstraction that reduces the analysis time without sacrificing the precision. This is unlike the existing cache analysing approaches where either precision or scalability (analysis time) is sacrificed. Experimental results are presented that demonstrate the practical applicability of this analysis.}},
    affiliation = {Robotics and Embedded Systems [M{\"u}nchen] , Department of Electrical and Computer Engineering [Auckland ] - ECE , SPADES - Inria Grenoble Rh{\^o}ne-Alpes , Compiler Design Lab},
    author = {Andalam, Sidharta and Sinha, Roopak and Roop, Partha S. and Girault, Alain and Reineke, Jan},
    hal_id = {hal-00781566},
    institution = {INRIA},
    keyword = {Instruction Cache Analysis, WCET, worst case execution analysis, direct mapped cache.},
    language = {Anglais},
    month = {Jan},
    number = {RR-8214},
    pages = {62 p.},
    pdf = {http://hal.inria.fr/hal-00781566/PDF/CacheAnalysisINRIAtechreport.pdf},
    type = {rapport de recherche},
    url = {http://hal.inria.fr/hal-00781566},
    year = {2013}
   }
   

5. Building Timing Predictable Embedded Systems
   P. Axer, R. Ernst, H. Falk, A. Girault, D. Grund, N. Guan, B. Jonsson, P. Marwedel, J. Reineke, C. Rochange, M. Sebastian, R. Hanxleden, R. Wilhelm, and W. Yi
   Technical Report, Uppsala University, Department of Information Technology, July 2012
   [pdf] [bib]

   @techreport{Falk12,
    title = {Building Timing Predictable Embedded Systems},
    author = {Axer, Philip and Ernst, Rolf and Falk, Heiko and Girault, Alain and Grund, Daniel and Guan, Nan and Jonsson, Bengt and Marwedel, Peter and Reineke, Jan and Rochange, Christine and Sebastian, Maurice and Hanxleden, Reinhard von and Wilhelm, Reinhard and Yi, Wang},
    institution = {Uppsala University, Department of Information Technology},
    month = {Jul},
    url = {http://www.it.uu.se/research/publications/reports/2012-013/2012-013-nc.pdf},
    year = {2012}
   }
   

6. Sensitivity of Cache Replacement Policies
   J. Reineke and D. Grund
   Technical Report, SFB/TR 14 AVACS, March 2008
   [pdf] [bib]

   @techreport{Reineke08a,
    title = {Sensitivity of Cache Replacement Policies},
    access = {open},
    author = {Reineke, Jan and Grund, Daniel},
    bibtex = {atr036.bib},
    editor = {Becker, Bernd and Damm, Werner and Fr\"anzle, Martin and Olderog, Ernst-R\"udiger and Podelski, Andreas and Wilhelm, Reinhard},
    institution = {SFB/TR 14 AVACS},
    month = {Mar},
    note = {ISSN: 1860-9821, http://www.avacs.org},
    number = {36},
    series = {ATR},
    subproject = {R2},
    type = {reports of sfb/tr 14 avacs},
    url = {http://www.avacs.org/Publikationen/Open/avacs_technical_report_036.pdf},
    year = {2008}
   }
   

7. Polynomial Precise Interval Analysis Revisited
   T. Gawlitza, J. Reineke, H. Seidl, and R. Wilhelm
   Technical Report, TU München, Germany, 2006
   [bib]

   @techreport{Gawlitza06,
    title = {Polynomial Precise Interval Analysis Revisited},
    author = {Gawlitza, Thomas and Reineke, Jan and Seidl, Helmut and Wilhelm, Reinhard},
    institution = {TU M\"unchen, Germany},
    year = {2006}
   }
   

8. Predictability of Cache Replacement Policies
   J. Reineke, D. Grund, C. Berg, and R. Wilhelm
   Technical Report, SFB/TR 14 AVACS, September 2006
   [pdf] [bib]

   @techreport{Reineke06a,
    title = {Predictability of Cache Replacement Policies},
    access = {open},
    author = {Reineke, Jan and Grund, Daniel and Berg, Christoph and Wilhelm, Reinhard},
    bibtex = {atr009.bib},
    editor = {Becker, Bernd and Damm, Werner and Fr\"anzle, Martin and Olderog, Ernst-R\"udiger and Podelski, Andreas and Wilhelm, Reinhard},
    institution = {SFB/TR 14 AVACS},
    month = {Sep},
    note = {ISSN: 1860-9821, http://www.avacs.org},
    number = {9},
    series = {ATR},
    subproject = {R2},
    type = {reports of sfb/tr 14 avacs},
    url = {http://www.avacs.org/Publikationen/Open/avacs_technical_report_009.pdf},
    year = {2006}
   }
   

PhD Thesis

1. Automatic Generation of Models of Microarchitectures
   Andreas Abel
   Universität des Saarlandes, 2020
   [pdf] [bib]

   @phdthesis{Abel20b,
    author = {Andreas Abel},
    title = {Automatic Generation of Models of Microarchitectures},
    school = {Universit\"at des Saarlandes},
    year = {2020},
    url = {https://d-nb.info/1212853466/34}
   }
   

2. On Static Execution-Time Analysis---Compositionality, Pipeline Abstraction, and Predictable Hardware
   Sebastian Hahn
   Universität des Saarlandes, 2019
   [pdf] [bib]

   @phdthesis{Hahn2019,
    author = {Sebastian Hahn},
    title = {On Static Execution-Time Analysis---Compositionality, Pipeline Abstraction, and Predictable Hardware},
    school = {Universit\"at des Saarlandes},
    year = {2019},
    url = {https://d-nb.info/1187241180/34}
   }
   

3. Caches in WCET Analysis
   J. Reineke
   Universität des Saarlandes, November 2008
   [pdf] [pdf slides] [bib]

   @phdthesis{Reineke08,
    title = {Caches in {WCET} Analysis},
    author = {Reineke, Jan},
    month = {Nov},
    school = {Universit\"at des Saarlandes},
    slides = {http://rw4.cs.uni-saarland.de/~reineke/talks/phdDefenseReineke.pdf},
    url = {http://rw4.cs.uni-saarland.de/~reineke/publications/DissertationCachesInWCETAnalysis.pdf},
    year = {2008}
   }
   

Masters Thesis

1. Characterising Input-Dependent Instruction Timing via Measurements
   L. Biehl
   Saarland University, 2021
   [bib]

   @mastersthesis{Biehl21,
    title = {Characterising Input-Dependent Instruction Timing via Measurements},
    author = {Biehl, Lucas},
    school = {Saarland University},
    type = {master thesis},
    url = {http://embedded.cs.uni-saarland.de/publications/theses/thesis_cs_msc_Biehl_Lucas_Alexander.pdf},
    year = {2021}
   }
   

2. Warping Cache Simulation of Polyhedral Programs
   C. Morelli
   Saarland University, 2021
   [bib]

   @mastersthesis{Morelli21,
    title = {Warping Cache Simulation of Polyhedral Programs},
    author = {Morelli, Canberk},
    school = {Saarland University},
    type = {master thesis},
    url = {http://embedded.cs.uni-saarland.de/publications/theses/thesis_cs_msc_Morelli_Canberk.pdf},
    year = {2021}
   }
   

3. An Executable Structural Operational Formal Semantics for Python
   M. Köhl
   Saarland University, 2020
   [bib]

   @mastersthesis{Koehl20,
    title = {An Executable Structural Operational Formal Semantics for Python},
    author = {K\"ohl, Maximilian A.},
    school = {Saarland University},
    type = {master thesis},
    url = {http://embedded.cs.uni-saarland.de/publications/theses/thesis_cs_msc_Koehl_Maximilian.pdf},
    year = {2020}
   }
   

4. Cache Persistence Analysis: Finally Exact
   G. Stock
   Saarland University, 2020
   [bib]

   @mastersthesis{Stock20,
    title = {Cache Persistence Analysis: Finally Exact},
    author = {Stock, Gregory},
    school = {Saarland University},
    type = {master thesis},
    url = {http://embedded.cs.uni-saarland.de/publications/theses/thesis_cs_msc_Stock_Gregory.pdf},
    year = {2020}
   }
   

5. Optimal Offline Scheduling for Multi-Core Systems with Dynamically Partitioned Caches
   D. Shah
   Universität des Saarlandes, Germany, 2019
   [pdf] [bib]

   @mastersthesis{Shah19,
    title = {Optimal Offline Scheduling for Multi-Core Systems with Dynamically Partitioned Caches},
    author = {Shah, Darshit},
    school = {Universit\"at des Saarlandes, Germany},
    type = {master thesis},
    url = {http://embedded.cs.uni-saarland.de/publications/ThesisShah2019.pdf},
    year = {2019}
   }
   

6. Multi-dimensional Auto-vectorization of Stencil Codes
   S. Sharma
   Universität des Saarlandes, Germany, 2019
   [pdf] [bib]

   @mastersthesis{Sharma19,
     title = {Multi-dimensional Auto-vectorization of Stencil Codes},
     author = {Sharma, Shrey},
     school = {Universit\"at des Saarlandes, Germany},
     type = {master thesis},
     url = {http://embedded.cs.uni-saarland.de/publications/ThesisSharma2019.pdf},
     year = {2019}
   }
   

7. Array-aware Cache Analysis for Write-through and Write-back Caches
   T. Blaß
   Universität des Saarlandes, Germany, December 2016
   [pdf] [bib]

   @mastersthesis{Blass16,
    title = {Array-aware Cache Analysis for Write-through and Write-back Caches},
    author = {Bla\ss , Tobias},
    month = {Dec},
    school = {Universit\"at des Saarlandes, Germany},
    url = {http://embedded.cs.uni-saarland.de/publications/ThesisBlass2016.pdf},
    year = {2016}
   }
   

8. Evaluating compositional timing analyses
   C. Faymonville
   Universität des Saarlandes, Germany, September 2015
   [pdf] [bib]

   @mastersthesis{Faymonville15,
    title = {Evaluating compositional timing analyses},
    author = {Faymonville, Claus},
    month = {Sep},
    school = {Universit\"at des Saarlandes, Germany},
    url = {http://embedded.cs.uni-saarland.de/publications/ThesisFaymonville2015.pdf},
    year = {2015}
   }
   

9. Defining Compositionalty in Execution Time Analysis
   S. Hahn
   Universität des Saarlandes, Germany, 2014
   [pdf] [bib]

   @mastersthesis{Hahn14,
    title = {Defining Compositionalty in Execution Time Analysis},
    author = {Hahn, Sebastian},
    school = {Universit\"at des Saarlandes, Germany},
    type = {master's thesis},
    year = {2014}
   }
   

10. Measurement-based Inference of the Cache Hierarchy
    A. Abel
    Universität des Saarlandes, Germany, 2012
    [pdf] [bib]

    @mastersthesis{Abel12b,
     title = {Measurement-based Inference of the Cache Hierarchy},
     author = {Abel, Andreas},
     school = {Universit\"at des Saarlandes, Germany},
     url = {http://embedded.cs.uni-saarland.de/literature/AndreasAbelMastersThesis.pdf},
     year = {2012}
    }
    

11. Shape Analysis of Sets
    J. Reineke
    Universität des Saarlandes, Germany, June 2005
    [pdf] [pdf slides] [bib]

    @mastersthesis{Reineke05,
     title = {Shape Analysis of Sets},
     author = {Reineke, Jan},
     month = {Jun},
     school = {Universit\"at des Saarlandes, Germany},
     slides = {http://rw4.cs.uni-saarland.de/~reineke/talks/shapeAnalysisOfSets.pdf},
     url = {http://drops.dagstuhl.de/opus/volltexte/2006/698/pdf/06000.ReinekeJan.Other.698.pdf},
     year = {2005}
    }
    

Bachelors Thesis

1. Micro-ops: Cycle-accurate measurements of the behavior of modern Intel x86 microprocessors
   L. Barth
   Saarland University, 2021
   [bib]

   @mastersthesis{Barth21,
    title = {Micro-ops: Cycle-accurate measurements of the behavior of modern Intel x86 microprocessors},
    author = {Barth, Leon},
    school = {Saarland University},
    type = {bachelor thesis},
    url = {http://embedded.cs.uni-saarland.de/publications/theses/thesis_es_bsc_Barth_Leon.pdf},
    year = {2021}
   }
   

2. Visualisierung der Ausführung von Microbenchmarks auf aktuellen Prozessoren
   T. Ganster
   Saarland University, 2021
   [bib]

   @mastersthesis{Ganster21,
    title = {Visualisierung der Ausf\"uhrung von Microbenchmarks auf aktuellen Prozessoren},
    author = {Ganster, Till},
    school = {Saarland University},
    type = {bachelor thesis},
    url = {http://embedded.cs.uni-saarland.de/publications/theses/thesis_es_bsc_Ganster_Till.pdf},
    year = {2021}
   }
   

3. On the Relation between Stack Histograms and Reuse Histograms
   P. Hennen
   Saarland University, 2021
   [bib]

   @mastersthesis{Hennen21,
    title = {On the Relation between Stack Histograms and Reuse Histograms},
    author = {Hennen, Pascal},
    school = {Saarland University},
    type = {bachelor thesis},
    url = {http://embedded.cs.uni-saarland.de/publications/theses/thesis_cs_bsc_Hennen_Pascal.pdf},
    year = {2021}
   }
   

4. Experimental evaluation of inaccuracies in cache persistence analysis
   C. Schäfer
   Saarland University, 2021
   [bib]

   @mastersthesis{Schaefer21,
    title = {Experimental evaluation of inaccuracies in cache persistence analysis},
    author = {Sch\"afer, Corinna},
    school = {Saarland University},
    type = {bachelor thesis},
    url = {http://embedded.cs.uni-saarland.de/publications/theses/thesis_cs_bsc_Schaefer_Corinna.pdf},
    year = {2021}
   }
   

5. Detecting Cache Side-Channel Vulnerabilities using Hardware Performance Counters
   A. Prysinski
   Saarland University, 2020
   [bib]

   @mastersthesis{Prysinski21,
    title = {Detecting Cache Side-Channel Vulnerabilities using Hardware Performance Counters},
    author = {Prysinski, Alexander},
    school = {Saarland University},
    type = {bachelor thesis},
    url = {http://embedded.cs.uni-saarland.de/publications/theses/thesis_cyber_bsc_Prysinski_Alexander.pdf},
    year = {2020}
   }
   

6. Towards Relational Cache Analysis
   S. Hahn
   Saarland University, 2011
   [bib]

   @mastersthesis{Hahn11,
    title = {Towards Relational Cache Analysis},
    author = {Hahn, Sebastian},
    url = {http://embedded.cs.uni-sb.de/publications/RelCanaBSC2011.pdf}, 
    school = {Saarland University},
    type = {bachelor's thesis},
    year = {2011}
   }
   

7. From Uppaal To Slab
   A. Abel
   Saarland University, 2009
   [bib]

   @mastersthesis{Abel09,
    title = {From Uppaal To Slab},
    author = {Abel, Andreas},
    school = {Saarland University},
    type = {bachelor thesis},
    url = {http://embedded.cs.uni-saarland.de/literature/AndreasAbelBachelorThesis.pdf},
    year = {2009}
   }
   

Other

1. Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
   A. Abel and J. Reineke
   arXiv, 2021
   [bib]

   @misc{abel2021accurate,
    title = {Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures},
    archiveprefix = {arXiv},
    howpublished = {arXiv},
    author = {Abel, Andreas and Reineke, Jan},
    eprint = {2107.14210},
    primaryclass = {cs.PF},
    year = {2021}
   }
   

2. Hardware-Software Contracts for Secure Speculation
   M. Guarnieri, B. Köpf, J. Reineke, and P. Vila
   arXiv, abs/2006.03841, 2020
   [bib]

   @article{Guarnieri20a,
    title = {Hardware-Software Contracts for Secure Speculation},
    archiveprefix = {arXiv},
    author = {Guarnieri, Marco and K{{\"o}}pf, Boris and Reineke, Jan and Vila, Pepe},
    bibsource = {dblp computer science bibliography, https://dblp.org},
    biburl = {https://dblp.org/rec/journals/corr/abs-2006-03841.bib},
    eprint = {2006.03841},
    journal = {CoRR},
    timestamp = {Fri, 12 Jun 2020 14:02:57 +0200},
    url = {https://arxiv.org/abs/2006.03841v2},
    volume = {abs/2006.03841},
    year = {2020}
   }
   

3. Flushgeist: Cache Leaks from Beyond the Flush
   P. Vila, A. Abel, M. Guarnieri, B. Köpf, and J. Reineke
   arXiv, abs/2005.13853, 2020
   [bib]

   @article{Vila20,
    title = {Flushgeist: Cache Leaks from Beyond the Flush},
    archiveprefix = {arXiv},
    author = {Vila, Pepe and Abel, Andreas and Guarnieri, Marco and K{{\"o}}pf, Boris and Reineke, Jan},
    bibsource = {dblp computer science bibliography, https://dblp.org},
    biburl = {https://dblp.org/rec/journals/corr/abs-2005-13853.bib},
    eprint = {2005.13853},
    journal = {CoRR},
    timestamp = {Wed, 03 Jun 2020 11:36:54 +0200},
    url = {https://arxiv.org/abs/2005.13853},
    volume = {abs/2005.13853},
    year = {2020}
   }
   

4. nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems
   A. Abel and J. Reineke
   arXiv, abs/1911.03282, 2019
   [bib]

   @article{Abel19b,
    title = {nanoBench: {A} Low-Overhead Tool for Running Microbenchmarks on x86 Systems},
    archiveprefix = {arXiv},
    author = {Abel, Andreas and Reineke, Jan},
    eprint = {1911.03282},
    journal = {CoRR},
    url = {http://arxiv.org/abs/1911.03282},
    volume = {abs/1911.03282},
    year = {2019}
   }
   

5. Cache Persistence Analysis: Finally Exact
   G. Stock, S. Hahn, and J. Reineke
   arXiv, abs/1909.04374, 2019
   [bib]

   @article{Stock19b,
    title = {Cache Persistence Analysis: Finally Exact},
    archiveprefix = {arXiv},
    author = {Stock, Gregory and Hahn, Sebastian and Reineke, Jan},
    eprint = {1909.04374},
    journal = {CoRR},
    url = {http://arxiv.org/abs/1909.04374},
    volume = {abs/1909.04374},
    year = {2019}
   }
   

6. uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
   A. Abel and J. Reineke
   arXiv, abs/1810.04610, 2018
   [bib]

   @article{Abel18b,
    title = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on {Intel} Microarchitectures},
    archiveprefix = {arXiv},
    author = {Abel, Andreas and Reineke, Jan},
    eprint = {1810.04610},
    journal = {CoRR},
    url = {http://arxiv.org/abs/1810.04610},
    volume = {abs/1810.04610},
    year = {2018}
   }
   

7. On the Incomparability of Cache Algorithms in Terms of Timing Leakage
   P. Cañones, B. Köpf, and J. Reineke
   arXiv, abs/1807.01240, 2018
   [bib]

   @article{Canones18b,
    title = {On the Incomparability of Cache Algorithms in Terms of Timing Leakage},
    archiveprefix = {arXiv},
    author = {Ca{{\~n}}ones, Pablo and K{{\"o}}pf, Boris and Reineke, Jan},
    eprint = {1807.01240},
    journal = {CoRR},
    url = {http://arxiv.org/abs/1807.01240},
    volume = {abs/1807.01240},
    year = {2018}
   }
   

8. SPECTECTOR: Principled Detection of Speculative Information Flows
   M. Guarnieri, B. Köpf, J. Morales, J. Reineke, and A. Sánchez
   arXiv, abs/1812.08639, 2018
   [bib]

   @article{Guarnieri18,
    title = {{SPECTECTOR:} Principled Detection of Speculative Information Flows},
    archiveprefix = {arXiv},
    author = {Guarnieri, Marco and K{{\"o}}pf, Boris and Morales, Jos{{\'e}} F. and Reineke, Jan and S{{\'a}}nchez, Andr{{\'e}}s},
    bibsource = {dblp computer science bibliography, https://dblp.org},
    biburl = {https://dblp.org/rec/bib/journals/corr/abs-1812-08639},
    eprint = {1812.08639},
    journal = {CoRR},
    timestamp = {Wed, 02 Jan 2019 14:40:18 +0100},
    url = {http://arxiv.org/abs/1812.08639},
    volume = {abs/1812.08639},
    year = {2018}
   }
   

9. Fast and exact analysis for LRU caches
   C. Maïza, V. Touzeau, D. Monniaux, and J. Reineke
   arXiv, abs/1811.01670, 2018
   [bib]

   @article{Maiza18,
    title = {Fast and exact analysis for {LRU} caches},
    archiveprefix = {arXiv},
    author = {Ma{\"{\i }}za, Claire and Touzeau, Valentin and Monniaux, David and Reineke, Jan},
    eprint = {1811.01670},
    journal = {CoRR},
    url = {http://arxiv.org/abs/1811.01670},
    volume = {abs/1811.01670},
    year = {2018}
   }
   

10. Keeping up with Real Time
    R. Wilhelm, J. Reineke, and S. Wegener
    Advances in Aeronautical Informatics, Technologies Towards Flight 4.0., 2018
    [doi] [bib]

    @incollection{Wilhelm18,
     title = {Keeping up with Real Time},
     author = {Wilhelm, Reinhard and Reineke, Jan and Wegener, Simon},
     booktitle = {Advances in Aeronautical Informatics, Technologies Towards Flight 4.0.},
     doi = {10.1007/978-3-319-75058-3_9},
     pages = {121--133},
     url = {https://doi.org/10.1007/978-3-319-75058-3_9},
     year = {2018}
    }
    

11. Security Analysis of Cache Replacement Policies
    P. Cañones, B. Köpf, and J. Reineke
    arXiv, abs/1701.06481, 2017
    [bib]

    @article{Canones17b,
     title = {Security Analysis of Cache Replacement Policies},
     archiveprefix = {arXiv},
     author = {Ca{{\~n}}ones, Pablo and K{{\"o}}pf, Boris and Reineke, Jan},
     eprint = {1701.06481},
     journal = {CoRR},
     url = {http://arxiv.org/abs/1701.06481},
     volume = {abs/1701.06481},
     year = {2017}
    }
    

12. Ascertaining Uncertainty for Efficient Exact Cache Analysis
    V. Touzeau, C. Maïza, D. Monniaux, and J. Reineke
    arXiv, abs/1709.10008, 2017
    [bib]

    @article{Touzeau17a,
     title = {Ascertaining Uncertainty for Efficient Exact Cache Analysis},
     archiveprefix = {arXiv},
     author = {Touzeau, Valentin and Ma{\"{\i }}za, Claire and Monniaux, David and Reineke, Jan},
     eprint = {1709.10008},
     journal = {CoRR},
     url = {http://arxiv.org/abs/1709.10008},
     volume = {abs/1709.10008},
     year = {2017}
    }
    

13. On the Smoothness of Paging Algorithms
    J. Reineke and A. Salinger
    arXiv, abs/1510.03362, 2015
    [bib]

    @article{Reineke15b,
     title = {On the Smoothness of Paging Algorithms},
     archiveprefix = {arXiv},
     author = {Reineke, Jan and Salinger, Alejandro},
     eprint = {1510.03362},
     journal = {CoRR},
     url = {http://arxiv.org/abs/1510.03362},
     volume = {abs/1510.03362},
     year = {2015}
    }
    

14. CacheAudit: A Tool for the Static Analysis of Cache Side Channels
    G. Doychev, D. Feld, B. Köpf, L. Mauborgne, and J. Reineke
    Cryptology ePrint Archive, Report 2013/253, 2013
    [pdf] [bib]

    @misc{Doychev13a,
     title = {CacheAudit: A Tool for the Static Analysis of Cache Side Channels},
     author = {Doychev, Goran and Feld, Dominik and K\"opf, Boris and Mauborgne, Laurent and Reineke, Jan},
     howpublished = {Cryptology ePrint Archive, Report 2013/253},
     note = {\url{http://eprint.iacr.org/}},
     pdf = {http://eprint.iacr.org/2013/253.pdf},
     year = {2013}
    }
    

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