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Andreas AbelReal-Time and Embedded Systems Lab |
Short CV
I am a postdoc at Saarland University in the group of Prof. Jan Reineke. My research interests include reverse engineering of microarchitectures, performance prediction, and security. I completed my PhD in June 2020 with a thesis entitled Automatic Generation of Models of Microarchitectures.Tools / Websites
As part of my research, I have developed the following tools and websites.uops.info
This website provides more than 400,000 pages with detailed latency, throughput, and port usage data for most x86 instructions on recent Intel and AMD microarchitectures. While such data is important for understanding, predicting, and optimizing the performance of software running on these microarchitectures, most of it is not documented in the official processor manuals.
Check it out at https://www.uops.info.
nanoBench
nanoBench is a Linux-based tool for running small microbenchmarks on recent Intel and AMD x86 CPUs. The microbenchmarks are evaluated using hardware performance counters. The reading of the performance counters is implemented in a way that incurs only minimal overhead.
Check it out at https://github.com/andreas-abel/nanoBench.
nanoBench Cache Analyzer
A collection of tools for analyzing undocumented cache properties using hardware performance counters.
Check it out at: https://github.com/andreas-abel/nanoBench/tree/master/tools/CacheAnalyzer.
Results are available at https://uops.info/cache.html.
MeMin
MeMin is a tool for minimizing incompletely specified Mealy machines.
Check it out here.
Teaching
Summer 2018, Summer 2019
- Basic Course: Systemarchitektur
Winter 2015/2016
Winter 2013/2014
Summer 2013
- Advanced Course: Design and Analysis of Real-Time Systems
Publications
• Conference and Workshop Papers • PhD Thesis • Masters Thesis • Bachelors Thesis • Other •
Conference and Workshop Papers
- nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems
A. Abel and J. Reineke
ISPASS, August 2020
[bib] - uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
A. Abel and J. Reineke
ASPLOS, 2019
[doi] [bib] - Gray-box Learning of Serial Compositions of Mealy Machines
A. Abel and J. Reineke
NFM, June 2016
[doi] [pdf] [bib] - MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy Machines
A. Abel and J. Reineke
ICCAD, 2015
[doi] [pdf] [bib] - Reverse Engineering of Cache Replacement Policies in Intel Microprocessors and Their Evaluation (poster abstract)
A. Abel and J. Reineke
ISPASS, March 2014
[pdf] [bib] - Measurement-based Modeling of the Cache Replacement Policy
A. Abel and J. Reineke
RTAS, April 2013
[pdf] [pdf slides] [ppt slides] [bib] - Impact of Resource Sharing on Performance and Performance Prediciton: A Survey
A. Abel, F. Benz, J. Doerfert, B. Dörr, S. Hahn, F. Haupenthal, M. Jacobs, A. Moin, J. Reineke, B. Schommer, and R. Wilhelm
CONCUR, August 2013
[doi] [pdf] [bib] - Automatic Cache Modeling by Measurements
A. Abel and J. Reineke
JRWRTC, November 2012
[pdf] [bib]
PhD Thesis
- Automatic Generation of Models of Microarchitectures
Andreas Abel
Universität des Saarlandes, 2020
[pdf] [bib]
Masters Thesis
- Measurement-based Inference of the Cache Hierarchy
A. Abel
Universität des Saarlandes, Germany, 2012
[pdf] [bib]
Bachelors Thesis
Other
- Flushgeist: Cache Leaks from Beyond the Flush
P. Vila, A. Abel, M. Guarnieri, B. Köpf, and J. Reineke
arXiv, abs/2005.13853, 2020
[bib] - nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems
A. Abel and J. Reineke
arXiv, abs/1911.03282, 2019
[bib] - uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
A. Abel and J. Reineke
arXiv, abs/1810.04610, 2018
[bib]