Andreas Abel

Real-Time and Embedded Systems Lab
Universität des Saarlandes
eMail:
LinkedIn: http://www.linkedin.com/in/andreasabel
Phone: +49 681 302 5573
Building: E 1 3 Room: 404
Coordinates: N 49.257833° E 7.045144°

Short CV

I am a postdoc at Saarland University in the group of Prof. Jan Reineke. My research interests include reverse engineering of microarchitectures, performance prediction, and security. I completed my PhD in June 2020 with a thesis entitled Automatic Generation of Models of Microarchitectures.

Tools / Websites

As part of my research, I have developed the following tools and websites.

uops.info

This website provides more than 400,000 pages with detailed latency, throughput, and port usage data for most x86 instructions on recent Intel and AMD microarchitectures. While such data is important for understanding, predicting, and optimizing the performance of software running on these microarchitectures, most of it is not documented in the official processor manuals.

Check it out at https://www.uops.info.

nanoBench

nanoBench is a Linux-based tool for running small microbenchmarks on recent Intel and AMD x86 CPUs. The microbenchmarks are evaluated using hardware performance counters. The reading of the performance counters is implemented in a way that incurs only minimal overhead.

Check it out at https://github.com/andreas-abel/nanoBench.

nanoBench Cache Analyzer

A collection of tools for analyzing undocumented cache properties using hardware performance counters.

Check it out at: https://github.com/andreas-abel/nanoBench/tree/master/tools/CacheAnalyzer.

Results are available at https://uops.info/cache.html.

MeMin

MeMin is a tool for minimizing incompletely specified Mealy machines.

Check it out here.

Teaching

Summer 2018, Summer 2019

Basic Course: Systemarchitektur

Publications

• Conference and Workshop Papers • PhD Thesis • Masters Thesis • Bachelors Thesis • Other •

Conference and Workshop Papers

uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
A. Abel and J. Reineke
ICS '22: 2022 International Conference on Supercomputing, Virtual Event, USA, June 27-30, 2022, 2022
[bib]

@inproceedings{Abel22,
 title = {{uiCA}: Accurate Throughput Prediction of Basic Blocks on Recent {Intel} Microarchitectures},
 author = {Abel, Andreas and Reineke, Jan},
 booktitle = {{ICS} '22: 2022 International Conference on Supercomputing, Virtual Event, USA, June 27-30, 2022},
  series = {ICS '22},
 editor = {Rauchwerger, Lawrence and Cameron, Kirk and Nikolopoulos, Dimitrios S. and Pnevmatikatos, Dionisios},
 pages = {1--12},
 publisher = {{ACM}},
 month = {June},
 year = {2022},
 url = {https://dl.acm.org/doi/pdf/10.1145/3524059.3532396}
}

DiffTune Revisited: A Simple Baseline for Evaluating Learned llvm-mca Parameters
Andreas Abel
Machine Learning for Computer Architecture and Systems 2022, 2022
[bib]

@inproceedings{Abel22b,
 title={{DiffTune} Revisited: A Simple Baseline for Evaluating Learned llvm-mca Parameters},
 author={Andreas Abel},
 booktitle={Machine Learning for Computer Architecture and Systems 2022},
 month = {June},
 year={2022},
 url={https://openreview.net/forum?id=dw4evoj6AE}
}

nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems
A. Abel and J. Reineke
ISPASS, August 2020
[bib]

@inproceedings{Abel20a,
 title = {nanoBench: {A} Low-Overhead Tool for Running Microbenchmarks on x86 Systems},
 author = {Abel, Andreas and Reineke, Jan},
 booktitle = {2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)},
 month = {Aug},
 year = {2020}
}

uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
A. Abel and J. Reineke
ASPLOS, 2019
[doi] [bib]

@inproceedings{Abel19a,
 title = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on {Intel} Microarchitectures},
 acmid = {3304062},
 address = {New York, NY, USA},
 author = {Abel, Andreas and Reineke, Jan},
 booktitle = {ASPLOS},
 doi = {10.1145/3297858.3304062},
 isbn = {978-1-4503-6240-5},
 location = {Providence, RI, USA},
 numpages = {14},
 pages = {673--686},
 publisher = {ACM},
 series = {ASPLOS '19},
 url = {http://doi.acm.org/10.1145/3297858.3304062},
 year = {2019}
}

Gray-box Learning of Serial Compositions of Mealy Machines
A. Abel and J. Reineke
NFM, June 2016
[doi] [pdf] [bib]

@inproceedings{Abel16,
 title = {Gray-box Learning of Serial Compositions of {Mealy} Machines},
 author = {Abel, Andreas and Reineke, Jan},
 booktitle = {Nasa Formal Methods Symposium},
 doi = {10.1007/978-3-319-40648-0_21},
 month = {Jun},
 year = {2016}
}

MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy Machines
A. Abel and J. Reineke
ICCAD, 2015
[doi] [pdf] [bib]

@inproceedings{Abel15,
 title = {{MeMin}: {SAT-based} Exact Minimization of Incompletely Specified {Mealy} Machines},
 author = {Abel, Andreas and Reineke, Jan},
 booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
 doi = {10.1109/ICCAD.2015.7372555},
 pages = {94--101},
 url = {http://dx.doi.org/10.1109/ICCAD.2015.7372555},
 year = {2015}
}

Reverse Engineering of Cache Replacement Policies in Intel Microprocessors and Their Evaluation (poster abstract)
A. Abel and J. Reineke
ISPASS, March 2014
[pdf] [bib]

@inproceedings{Abel14,
 title = {Reverse Engineering of Cache Replacement Policies in {Intel} Microprocessors and Their Evaluation},
 author = {Abel, Andreas and Reineke, Jan},
 booktitle = {2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)},
 month = {Mar},
 pages = {141-142},
 url = {http://embedded.cs.uni-saarland.de/publications/ISPASS14.pdf},
 year = {2014}
}

Measurement-based Modeling of the Cache Replacement Policy
A. Abel and J. Reineke
RTAS, April 2013
[pdf] [pdf slides] [ppt slides] [bib]

@inproceedings{Abel13,
 title = {Measurement-based Modeling of the Cache Replacement Policy},
 author = {Abel, Andreas and Reineke, Jan},
 booktitle = {19th {IEEE} Real-Time and Embedded Technology and Applications Symposium, {RTAS} 2013, Philadelphia, PA, USA, April 9-11, 2013},
 month = {Apr},
 pages = {65--74},
 slides = {http://embedded.cs.uni-saarland.de/presentations/LearningCacheModels.pptx},
 slidespdf = {http://embedded.cs.uni-saarland.de/presentations/LearningCacheModels.pdf},
 url = {http://embedded.cs.uni-saarland.de/publications/CacheModelingRTAS2013.pdf},
 year = {2013}
}

Impact of Resource Sharing on Performance and Performance Prediction: A Survey
A. Abel, F. Benz, J. Doerfert, B. Dörr, S. Hahn, F. Haupenthal, M. Jacobs, A. Moin, J. Reineke, B. Schommer, and R. Wilhelm
CONCUR, August 2013
[doi] [pdf] [bib]

@inproceedings{Abel13b,
 title = {Impact of Resource Sharing on Performance and Performance Prediction: {A} Survey},
 author = {Abel, Andreas and Benz, Florian and Doerfert, Johannes and D\"orr, Barbara and Hahn, Sebastian and Haupenthal, Florian and Jacobs, Michael and Moin, Amir H. and Reineke, Jan and Schommer, Bernhard and Wilhelm, Reinhard},
 booktitle = {{CONCUR} 2013 - Concurrency Theory - 24th International Conference, {CONCUR} 2013, Buenos Aires, Argentina, August 27-30, 2013. Proceedings},
 doi = {10.1007/978-3-642-40184-8_3},
 month = {Aug},
 pages = {25--43},
 url = {http://embedded.cs.uni-saarland.de/publications/ResourceSharingSurvey.pdf},
 year = {2013}
}

Automatic Cache Modeling by Measurements
A. Abel and J. Reineke
JRWRTC, November 2012
[pdf] [bib]

@inproceedings{Abel12,
 title = {Automatic Cache Modeling by Measurements},
 author = {Abel, Andreas and Reineke, Jan},
 booktitle = {6th Junior Researcher Workshop on Real-Time Computing (in conjunction with RTNS)},
 month = {Nov},
 url = {http://embedded.cs.uni-saarland.de/publications/CacheModelingJRWRTC.pdf},
 year = {2012}
}

PhD Thesis

Automatic Generation of Models of Microarchitectures
Andreas Abel
Universität des Saarlandes, 2020
[pdf] [bib]

@phdthesis{Abel20b,
 author = {Andreas Abel},
 title = {Automatic Generation of Models of Microarchitectures},
 school = {Universit\"at des Saarlandes},
 year = {2020},
 url = {https://d-nb.info/1212853466/34}
}

Masters Thesis

Measurement-based Inference of the Cache Hierarchy
A. Abel
Universität des Saarlandes, Germany, 2012
[pdf] [bib]

@mastersthesis{Abel12b,
 title = {Measurement-based Inference of the Cache Hierarchy},
 author = {Abel, Andreas},
 school = {Universit\"at des Saarlandes, Germany},
 url = {http://embedded.cs.uni-saarland.de/literature/AndreasAbelMastersThesis.pdf},
 year = {2012}
}

Bachelors Thesis

From Uppaal To Slab
A. Abel
Saarland University, 2009
[bib]

@mastersthesis{Abel09,
 title = {From Uppaal To Slab},
 author = {Abel, Andreas},
 school = {Saarland University},
 type = {bachelor thesis},
 url = {http://embedded.cs.uni-saarland.de/literature/AndreasAbelBachelorThesis.pdf},
 year = {2009}
}

Other

Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
A. Abel and J. Reineke
arXiv, 2021
[bib]

@misc{abel2021accurate,
 title = {Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures},
 archiveprefix = {arXiv},
 howpublished = {arXiv},
 author = {Abel, Andreas and Reineke, Jan},
 eprint = {2107.14210},
 primaryclass = {cs.PF},
 year = {2021}
}

Flushgeist: Cache Leaks from Beyond the Flush
P. Vila, A. Abel, M. Guarnieri, B. Köpf, and J. Reineke
arXiv, abs/2005.13853, 2020
[bib]

@article{Vila20,
 title = {Flushgeist: Cache Leaks from Beyond the Flush},
 archiveprefix = {arXiv},
 author = {Vila, Pepe and Abel, Andreas and Guarnieri, Marco and K{{\"o}}pf, Boris and Reineke, Jan},
 bibsource = {dblp computer science bibliography, https://dblp.org},
 biburl = {https://dblp.org/rec/journals/corr/abs-2005-13853.bib},
 eprint = {2005.13853},
 journal = {CoRR},
 timestamp = {Wed, 03 Jun 2020 11:36:54 +0200},
 url = {https://arxiv.org/abs/2005.13853},
 volume = {abs/2005.13853},
 year = {2020}
}

nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems
A. Abel and J. Reineke
arXiv, abs/1911.03282, 2019
[bib]

@article{Abel19b,
 title = {nanoBench: {A} Low-Overhead Tool for Running Microbenchmarks on x86 Systems},
 archiveprefix = {arXiv},
 author = {Abel, Andreas and Reineke, Jan},
 eprint = {1911.03282},
 journal = {CoRR},
 url = {http://arxiv.org/abs/1911.03282},
 volume = {abs/1911.03282},
 year = {2019}
}

uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
A. Abel and J. Reineke
arXiv, abs/1810.04610, 2018
[bib]

@article{Abel18b,
 title = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on {Intel} Microarchitectures},
 archiveprefix = {arXiv},
 author = {Abel, Andreas and Reineke, Jan},
 eprint = {1810.04610},
 journal = {CoRR},
 url = {http://arxiv.org/abs/1810.04610},
 volume = {abs/1810.04610},
 year = {2018}
}

Real-Time and Embedded Systems Lab