Real-Time and Embedded Systems Lab

Jan Reineke

Real-Time and Embedded Systems Lab
Saarland University
Saarland Informatics Campus
Phone: +49 681 302 4448
eMail:
Building: E 1 3 Room: 410
Coordinates: N 49.257833° E 7.045144°

Administrative Assistant: Sandra Neumann
Phone: +49 681 302 3434
Building: E 1 3 Room: 430

Office Hour: Wednesday 16:00-17:00 (please send me an email, as I may be travelling; other times are possible)

I am looking for PhD students and postdocs to work on safety and security problems at the hardware-software interface!
Possible research topics are flexible and include but are not limited to:

Static program analysis of real-time and security properties

Design of timing-predictable microarchitectures

Design of secure microarchitectures

Formal verification of hardware w.r.t. hardware-software contracts

If you are interested, please feel free to . My work is generously supported by an ERC Advanced Grant.

I am always looking for student assistants.
If you are interested in working with me and my group or if you are looking for a Bachelor or Master thesis topic, please feel free to stop by my office or to drop me an email.

Short CV

Jan Reineke is a professor of computer science at Saarland University. Before joining Saarland University in 2012, he has been a postdoctoral scholar at UC Berkeley in the Ptolemy group from 2009 to 2011. He completed his MSc and PhD in Computer Science at Saarland University in 2005 and 2008, respectively, and his BSc in Computing Science at the University of Oldenburg in 2003.

His research centers around problems at the boundary between hardware and software.

In the area of real-time systems, he is particularly interested in principles for the design of timing-predictable hardware and in precise and efficient timing-analysis techniques for multi-core architectures. His recent results include the design of the first provably timing-predictable pipelined processor design (RTSS 2018) and the first exact analyses for LRU caches (CAV 2017, POPL 2019, RTSS 2019).

Another focus of his work are security vulnerabilities of hardware-software systems. Recent results include the development of automatic techniques to detect information leaks introduced by speculative execution (Spectector, S&P 2020), techniques to quantify the information leakage through cache side channels (ACM TISSEC 2015), and automatic methods to obtain highly detailed performance models for modern microarchitectures (uops.info, ASPLOS 2019).

In 2012, he was selected as an Intel Early Career Faculty Honor Program awardee. He was the PC chair of EMSOFT 2014, the International Conference on Embedded Software, a Topic co-chair at DATE 2016 and the PC chair of WCET 2017, the International Workshop on Worst-Case Execution Time Analysis. His papers have been awarded 9 outstanding paper awards and two best-paper nominations, most recently at DATE (2024), CCS (2023), RTSS (2023, 2019, 2018), Oakland (2021), and ECRTS (2017). In 2021, he has been awarded an ERC Advanced Grant.

Selected Recent Publications

Journal Papers

Fast and Exact Analysis for LRU Caches
V. Touzeau, C. Maïza, D. Monniaux, and J. Reineke
Proc. ACM Program. Lang., 3(POPL), January 2019
[doi] [bib]

@article{Touzeau19,
 title = {Fast and Exact Analysis for LRU Caches},
 acmid = {3290367},
 address = {New York, NY, USA},
 articleno = {54},
 author = {Touzeau, Valentin and Ma\"{\i }za, Claire and Monniaux, David and Reineke, Jan},
 doi = {10.1145/3290367},
 issn = {2475-1421},
 issue_date = {January 2019},
 journal = {Proc. ACM Program. Lang.},
 keyword = {Abstract Interpretation, Cache Analysis, LRU},
 month = {Jan},
 number = {POPL},
 numpages = {29},
 pages = {54:1--54:29},
 publisher = {ACM},
 url = {http://doi.acm.org/10.1145/3290367},
 volume = {3},
 year = {2019}
}

An extensible framework for multicore response time analysis
R. Davis, S. Altmeyer, L. Indrusiak, C. Maiza, V. Nelis, and J. Reineke
Real-Time Systems, 54(3), July 2018
[doi] [bib]

@article{Davis18a,
 title = {An extensible framework for multicore response time analysis},
 abstract = {In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on context-independent WCET values. Instead, the analysis formulates response times directly from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.},
 author = {Davis, Robert I. and Altmeyer, Sebastian and Indrusiak, Leandro S. and Maiza, Claire and Nelis, Vincent and Reineke, Jan},
 day = {01},
 doi = {10.1007/s11241-017-9285-4},
 issn = {1573-1383},
 journal = {Real-Time Systems},
 month = {Jul},
 number = {3},
 pages = {607--661},
 url = {https://doi.org/10.1007/s11241-017-9285-4},
 volume = {54},
 year = {2018}
}

The Semantic Foundations and a Landscape of Cache-Persistence Analyses
J. Reineke
LITES, 5(1), 2018
[doi] [bib]

@article{Reineke18a,
 title = {The Semantic Foundations and a Landscape of Cache-Persistence Analyses},
 author = {Reineke, Jan},
 doi = {10.4230/LITES-v005-i001-a003},
 journal = {{LITES}},
 number = {1},
 pages = {03:1--03:52},
 url = {https://doi.org/10.4230/LITES-v005-i001-a003},
 volume = {5},
 year = {2018}
}

CacheAudit: A Tool for the Static Analysis of Cache Side Channels
G. Doychev, B. Köpf, L. Mauborgne, and J. Reineke
ACM Trans. Inf. Syst. Secur., 18(1), June 2015
[doi] [pdf] [bib]

@article{Doychev15,
 title = {{CacheAudit}: A Tool for the Static Analysis of Cache Side Channels},
 acmid = {2756550},
 address = {New York, NY, USA},
 articleno = {4},
 author = {Doychev, Goran and K{\"o}pf, Boris and Mauborgne, Laurent and Reineke, Jan},
 doi = {10.1145/2756550},
 issn = {1094-9224},
 issue_date = {June 2015},
 journal = {ACM Trans. Inf. Syst. Secur.},
 keyword = {Side-channel attacks, caches},
 month = {Jun},
 number = {1},
 numpages = {32},
 pages = {4:1--4:32},
 publisher = {ACM},
 url = {http://doi.acm.org/10.1145/2756550},
 volume = {18},
 year = {2015}
}

Towards compositionality in execution time analysis: definition and challenges
S. Hahn, J. Reineke, and R. Wilhelm
SIGBED Review, 12(1), 2015
[doi] [bib]

@article{Hahn15,
 title = {Towards compositionality in execution time analysis: definition and challenges},
 author = {Hahn, Sebastian and Reineke, Jan and Wilhelm, Reinhard},
 bibsource = {dblp computer science bibliography, http://dblp.org},
 biburl = {http://dblp.uni-trier.de/rec/bib/journals/sigbed/0001RW15},
 doi = {10.1145/2752801.2752805},
 journal = {{SIGBED} Review},
 number = {1},
 pages = {28--36},
 timestamp = {Sat, 25 Apr 2015 19:50:05 +0200},
 url = {http://doi.acm.org/10.1145/2752801.2752805},
 volume = {12},
 year = {2015}
}

Conference and Workshop Papers

Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors (Best Paper Award Candidate )
G. Mohr, M. Guarnieri, and J. Reineke
DATE, March 2024
[bib]

@inproceedings{Mohr24,
 title = {Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors},
 author = {Mohr, Gideon and Guarnieri, Marco and Reineke, Jan},
 booktitle = {Design, Automation and Test in Europe Conference and Exhibition (DATE), 2024},
 month = {Mar},
 organization = {IEEE},
 year = {2024}
}

Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis (Outstanding Paper Award )
V. Touzeau and J. Reineke
RTSS, 2023
[bib]

@inproceedings{Touzeau23,
 title = {Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis},
 author = {Touzeau, Valentin and Reineke, Jan},
 booktitle = {2023 {IEEE} Real-Time Systems Symposium, {RTSS} 2023, Taipei, Taiwan, December 5-8, 2023},
 year = {2023}
}

Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts (Distinguished Paper Award at CCS 2023 and Intel Hardware Security Academic Award Finalist )
Z. Wang, G. Mohr, K. Gleissenthall, J. Reineke, and M. Guarnieri
CCS, 2023
[bib]

@inproceedings{wang2023specification,
 title = {Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts},
 author = {Wang, Zilong and Mohr, Gideon and Gleissenthall, Klaus von and Reineke, Jan and Guarnieri, Marco},
 booktitle = {Proceedings of the 30th ACM Conference on Computer and Communications Security},
 publisher = {ACM},
 series = {CCS 2023},
 year = {2023}
}

uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
A. Abel and J. Reineke
ICS, 2022
[bib]

@inproceedings{Abel22,
 title = {{uiCA}: Accurate Throughput Prediction of Basic Blocks on Recent {Intel} Microarchitectures},
 author = {Abel, Andreas and Reineke, Jan},
 booktitle = {{ICS} '22: 2022 International Conference on Supercomputing, Virtual Event, USA, June 27-30, 2022},
  series = {ICS '22},
 editor = {Rauchwerger, Lawrence and Cameron, Kirk and Nikolopoulos, Dimitrios S. and Pnevmatikatos, Dionisios},
 pages = {1--12},
 publisher = {{ACM}},
 month = {June},
 year = {2022},
 url = {https://dl.acm.org/doi/pdf/10.1145/3524059.3532396}
}

Warping Cache Simulation of Polyhedral Programs
C. Morelli and J. Reineke
PLDI, June 2022
[doi] [bib]

@inproceedings{Morelli22,
 title = {Warping Cache Simulation of Polyhedral Programs},
 address = {New York, NY, USA},
 author = {Morelli, Canberk and Reineke, Jan},
 booktitle = {PLDI},
 doi = {10.1145/3519939.3523714},
 isbn = {978-1-4503-9265-5/22/06},
 location = {San Diego, CA, USA},
 numpages = {16},
 publisher = {ACM},
 series = {PLDI '22},
 url = {http://doi.acm.org/10.1145/3519939.3523714},
 month = {Jun},
 year = {2022},
}

Hardware-Software Contracts for Secure Speculation (Best Paper Award )
M. Guarnieri, B. Köpf, J. Reineke, and P. Vila
S&P (Oakland), May 2021
[bib]

@inproceedings{Guarnieri21,
 title = {Hardware-Software Contracts for Secure Speculation},
 author = {Guarnieri, Marco and K{{\"o}}pf, Boris and Reineke, Jan and Vila, Pepe},
 booktitle = {2021 {IEEE} Symposium on Security and Privacy, {SP} 2021, Proceedings, San Francisco, California, {USA}},
 month = {May},
 url = {https://arxiv.org/abs/2006.03841},
 year = {2021}
}

SPECTECTOR: Principled Detection of Speculative Information Flows
M. Guarnieri, B. Köpf, J. Morales, J. Reineke, and A. Sánchez
S&P (Oakland), May 2020
[pdf] [bib]

@inproceedings{Guarnieri20,
 title = {{SPECTECTOR:} Principled Detection of Speculative Information Flows},
 author = {Guarnieri, Marco and K{{\"o}}pf, Boris and Morales, Jos{{\'e}} F. and Reineke, Jan and S{{\'a}}nchez, Andr{{\'e}}s},
 booktitle = {2020 {IEEE} Symposium on Security and Privacy, {SP} 2020, Proceedings, San Francisco, California, {USA}},
 month = {May},
 url = {https://spectector.github.io/papers/spectector.pdf},
 year = {2020}
}

uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
A. Abel and J. Reineke
ASPLOS, 2019
[doi] [bib]

@inproceedings{Abel19a,
 title = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on {Intel} Microarchitectures},
 acmid = {3304062},
 address = {New York, NY, USA},
 author = {Abel, Andreas and Reineke, Jan},
 booktitle = {ASPLOS},
 doi = {10.1145/3297858.3304062},
 isbn = {978-1-4503-6240-5},
 location = {Providence, RI, USA},
 numpages = {14},
 pages = {673--686},
 publisher = {ACM},
 series = {ASPLOS '19},
 url = {http://doi.acm.org/10.1145/3297858.3304062},
 year = {2019}
}

Cache Persistence Analysis: Finally Exact (Best Paper Award )
G. Stock, S. Hahn, and J. Reineke
RTSS, December 2019
[bib]

@inproceedings{Stock19,
 title = {Cache Persistence Analysis: Finally Exact},
 author = {Stock, Gregory and Hahn, Sebastian and Reineke, Jan},
 booktitle = {RTSS},
 month = {Dec},
 year = {2019}
}

Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core (Best Student Paper Award )
S. Hahn and J. Reineke
RTSS, December 2018
[pdf] [pdf slides] [bib]

@inproceedings{Hahn18,
 title = {Design and Analysis of {SIC}: A Provably Timing-Predictable Pipelined Processor Core},
 author = {Hahn, Sebastian and Reineke, Jan},
 booktitle = {RTSS},
 month = {Dec},
 year = {2018}
}

Publications

A list of all of my publications can be found here and on DBLP.

Recent and Upcoming Professional Activities

RTAS 2014 (Track 2), 2015 (Track 1), 2016 (Track 3), 2018 (Track 3), 2019 (Track 3), 2020 (Track 1), 2022 (PC Member)
EMSOFT 2015, 2021 (PC Member)
CAV 2020 (PC Member)
MEMOCODE 2019 (PC Member)
WCET 2017 (PC Chair), 2018, 2019, 2022 (PC Member), 2018-ongoing (Steering Committee)
FORMATS 2017 (PC Member)
ECRTS 2017, 2018, 2021, 2022, 2023 (PC Member)
RTSS 2016, 2017, 2020 (PC Member)
RTNS 2016 (PC Member)
DATE 2016 (PC Topic Co-Chair)
DATE 2015, 2016 (PC Member)
EMSOFT 2014 (PC Co-Chair)