Jan Reineke

Real-Time and Embedded Systems Lab
Saarland University
Saarland Informatics Campus
Phone: +49 681 302 4448
Building: E 1 3 Room: 410
Coordinates: N 49.257833° E 7.045144°

Office Hour: Wednesday 16:00-17:00

I have funding from Intel for graduate students and/or postdocs to work on rigorously fixing speculative-execution vulnerabilities, such as Spectre, using static analysis and compiler techniques.
If you are familiar with formal methods and have knowledge of modern microarchitectural features such as speculation and out-of-order execution, please feel free to contact me.

I am always looking for student assistants.
If you are interested in working with me and my group or if you are looking for a Bachelor or Master thesis topic, please feel free to stop by my office or to drop me an email.

Short CV

Jan Reineke is a professor of computer science at Saarland University. Before joining Saarland University in 2012, he has been a postdoctoral scholar at UC Berkeley in the Ptolemy group from 2009 to 2011. He completed his MSc and PhD in Computer Science at Saarland University in 2005 and 2008, respectively, and his BSc in Computing Science at the University of Oldenburg in 2003.

His research centers around problems at the boundary between hardware and software.

In the area of real-time systems, he is particularly interested in principles for the design of timing-predictable hardware and in precise and efficient timing-analysis techniques for multi-core architectures. His recent results include the design of the first provably timing-predictable pipelined processor design (RTSS 2018) and the first exact analyses for LRU caches (CAV 2017, POPL 2019).

Another focus of his work are security vulnerabilities of hardware-software systems. Recent results include the development of automatic techniques to detect information leaks introduced by speculative execution (Spectector), techniques to quantify the information leakage through cache side channels (ACM TISSEC 2015), and automatic methods to obtain highly detailed performance models for modern microarchitectures (ASPLOS 2019).

In 2012, he was selected as an Intel Early Career Faculty Honor Program awardee. He was the PC chair of EMSOFT 2014, the International Conference on Embedded Software, a Topic co-chair at DATE 2016 and the PC chair of WCET 2017, the International Workshop on Worst-Case Execution Time Analysis. His papers have been awarded 5 outstanding paper awards and one best-paper nomination at conferences including RTSS and ECRTS.

Selected Recent Publications


A list of all of my publications can be found here and on DBLP.

Recent and Upcoming Professional Activities