Hardware Design Seminar/Proseminar
OrganizersJan Reineke, Sebastian Hahn
- Initial Meeting: The initial meeting will take place on Thursday, 18th October, 12-14h (c.t.), in room 401 in building E1 3. You have to attend the first meeting if you want to participate in this seminar.
- Weekly Meeting: The time slot for the weekly meeting will be determined at the initial meeting.
In this seminar/proseminar you will learn about various aspects of modern microarchitectures, ranging from performance-enhancing features like pipelining and caches to the implementation of interrupts and virtual memory.
Groups of 2 to 3 students will form teams and collaborate to add a particular microarchitectural feature to a basic RISC-V processor design that will be provided by the organizers at the beginning of the semester.
The implementation will be carried out in the hardware description language Verilog/SystemVerilog. Thus besides learning about features of modern processors, you will also gain valuable practical skills that will enable you to create your own hardware designs and to program FPGAs!
We expect participants of the seminar to be familiar with basic concepts in computer architecture (e.g. in-order pipelining). Furthermore, basic knowledge of the Verilog hardware description language is required. Knowledge of at least one RISC-like instruction set architecture (e.g. MIPS, ARM, RISC-V) is a plus.
Passing the undergraduate course Systemarchitektur is sufficient to satisfy these prerequisites.
List of TopicsBelow you will find a list of suggested topics. The topics labelled advanced are more challenging but also more interesting. We will take the difficulty of these topics into account when grading. If you are interested in implementing an aspect not listed below, please let us know! We are open to suggestions.
- Interrupts: add a basic interrupt mechanism to the processor to enable efficient handling of I/O and to enable preemptive scheduling.
- Virtual memory: add support for efficient paging to the processor, including TLBs.
- Floating-point unit: incrementally construct a floating-point unit (FPU) and add floating-point instructions to the processor to use the FPU.
- DRAM controller: design and build a memory controller to access the DRAM chips; evaluate the impact of design choices on the controller's performance.
- Out-of-order execution (advanced): enhance our implementation of Tomasulo's algorithm for dynamic scheduling of instructions; implement speculation, branch prediction, speculative memory accesses; if time permits, demonstrate that the implementation is vulnerable to the infamous SPECTRE attack.
- Multi-core with caches and shared memory (advanced): implement a multi-core system based on the provided single cores; implement cache coherency protocol; implement ISA-extension A (atomic) to support synchronisation.
- Beginning of the term: Students choose topics and teams are formed.
- Reading of background material, mostly from textbooks, possibly from research papers, and initial experiments.
- Students work out a concrete project plan and identify challenges: first presentation of projects after 6 to 8 weeks.
- Implementation phase. Implementation of project plan. Perform extensive simulations. An FPGA board will be provided for experiments if needed.
- Final project presentation at the end of the term:
- Written report
- 15-minute team presentation
- 10-minute presentation by each team member discussing their contributions
- Practical demonstration of project outcomes
The seminar can be taken both as a 7 credit-point seminar or as a 5 credit-point proseminar. The workload will then be adjusted accordingly.
RegistrationIf you would like to participate in this seminar, please send us an email (in German or English) in which you:
- Mention 3 topics in decreasing order of interest or propose a topic of your own!
- State, whether you would like to take the course as a seminar (7 CP) or a proseminar (5 CP).
- If applicable, mention fellow students who you would like to form a team with.
- Provide your name and matriculation number.
- Briefly state why you are motivated to participate in this particular seminar!
- An introduction to Verilog and SystemVerilog can be found at ASIC World.
- We will use Altera FPGAs during this seminar. To synthesize and upload (System)Verilog-Code to an FPGA, you will need the synthesis software Quartus. You can obtain a free copy of Quartus Prime Lite from the Intel Download Center. This package includes precise technology information of our FPGA Chip (Cyclone IV) and the powerful simulation tool ModelSim.
- Background information on the RISC-V instruction set architecture can be found here.