Hardware Design Seminar/Proseminar
OrganizersJan Reineke, Sebastian Hahn
- Weekly Meeting: The time slot for weekly meeting (either all participants or smaller groups) is set to thursdays from 10 to 12 am in room 401 in building E1 3.
In this seminar/proseminar you will learn about various aspects of modern microarchitectures, ranging from performance-enhancing features like pipelining and caches to the implementation of interrupts and virtual memory.
Groups of 2 to 3 students will form teams and collaborate to add a particular microarchitectural feature to a basic ARM processor design that will be provided by the organizers at the beginning of the semester.
The implementation will be carried out in the hardware description language Verilog/SystemVerilog. Thus besides learning about features of modern processors, you will also gain valuable practical skills that will enable you to create your own hardware designs and to program FPGAs!
List of TopicsBelow you will find a list of suggested topics. If you are interested in implementing an aspect not listed below, please let us know! We are open to suggestions.
- Strictly in-order pipeline: a variant of an in-order pipeline particularly suited for use in hard real-time systems. Find out more in the following paper.
- Caches: implement set-associative instruction and data caches, experiment with different write and replacement policies.
- Interrupts: add a basic interrupt mechanism to the processor to enable efficient handling of I/O and to enable preemptive scheduling.
- Virtual memory: add support for paging to the processor.
- Floating-point unit: incrementally construct a floating-point unit (FPU) and add floating-point instructions to the processor to use the FPU.
- Memory-mapped I/O: add support for memory-mapped I/O to enable graphics and sound outputs as well as inputs via a keyboard, joystick, or an SD card.
- Limited out-of-order execution (advanced!): implement a limited form of out-of-order execution, where long-running memory instructions may be overtaken by other instructions.
- Out-of-order execution (advanced!): implement Tomasulo's algorithm for dynamic scheduling of instructions.
- Beginning of the term: Students choose topics and teams are formed.
- Reading of background material, mostly from textbooks, possibly from research papers, and initial experiments.
- Students work out a concrete project plan and identify challenges: first presentation of projects after 6 to 8 weeks.
- Implementation phase. An FPGA board will be provided for experimentation.
- Final project presentation at the end of the term:
- 15-minute team presentation
- 10-minute presentation by each team member discussing their contributions
- Practical demonstration of project outcomes
The seminar can be taken both as a 7 credit-point seminar or as a 5 credit-point proseminar. The workload will then be adjusted accordingly.
RegistrationIf you would like to participate in this seminar, please send us an email in which you:
- Mention 3 topics in decreasing order of interest or propose a topic of your own!
- State, whether you would like to take the course as a seminar (7 CP) or a proseminar (5 CP).
- If applicable, mention fellow students who you would like to form a team with.
- Provide your name and matriculation number.
- Briefly state why you are motivated to participate in this particular seminar!
- An introduction to Verilog and SystemVerilog can be found at ASIC World.
- We will use Altera FPGAs during this seminar. To synthesize and upload (System)Verilog-Code to an FPGA, you will need the synthesis software Quartus. You can obtain a free copy of Quartus Lite from the Altera Download Center. This package includes precise technology information of our FPGA Chip (Cyclone IV) and the powerful simulation tool ModelSim.