Welcome to the Real-Time and Embedded Systems Lab at Saarland University!
ResearchWe study the modeling and design of embedded real-time systems.
A focus of our group is on identifying existing and designing new, predictable, yet efficient microarchitectural components suitable for use in hard real-time scenarios. For such components we develop sound, precise and efficient static analyses based on abstract interpretation.
- October 2016: Our paper on "Analysis of Write-back Caches under Fixed-priority Preemptive and Non-preemptive Scheduling" has been named an Outstanding Paper at RTNS 2016!
- September 2016: Our papers "Enabling Compositionality for Multicore Timing Analysis" and "Analysis of Write-back Caches under Fixed-priority Preemptive and Non-preemptive Scheduling" have been accepted at RTNS 2016.
- June 2016: Our survey article on cache analysis has appeared in the Leibniz Transactions on Embedded Systems.
- June 2016: Consider submitting a paper to RTNS 2016, which will take place in Brest this year.
- June 2016: Jan is a panelist at DAC on Predictable System Timing – Probab(ilistical)ly?
- April 2016: Our paper "Gray-box Learning of Serial Compositions of Mealy Machines" has been accepted at the NASA Formal Methods Symposium 2016.
- March 2016: Our DFG project proposal "PEP: Precise and Efficient Prediction of Good Worst-case Performance for Contemporary and Future Architectures" has been granted!
- February 2016: Our paper "MIRROR: Symmetric Timing Analysis for Real-Time Tasks on Multicore Platforms with Shared Resources" with coauthors Wen-Hung Huang and Jian-Jia Chen has been accepted at DAC 2016.
- January 2016: We welcome Giovanni Meciani, who joins our group for six months as part of an ERASMUS+ traineeship!
- November 2015: Our paper on A Generic and Compositional Framework for Multicore Response Time Analysis appears at RTNS 2015 and has been named an Outstanding Paper!
- October 2015: Jan is giving an invited talk about cache-related preemption delay at TELECOM ParisTech.
- September 2015: We report on progress concerning timing-predictable processor pipelines in a Festschrift article on the occasion of Ernst-Rüdiger Olderog's 60th birthday.
- August 2015: Consider submitting a paper to RTAS 2016.
- August 2015: Consider submitting a paper to DATE 2016.
- July 2015: Our paper on the smoothness of paging algorithms has been accepted at WAOA 2015.
- June 2015: Our article on quantifying cache side channels has appeared in the ACM Transactions on Information and System Security.
- June 2015: Our tool paper on ASTRA has been accepted at SPIN 2015.
- June 2015: Our paper on the minimization of incompletely-specified Mealy machines has been accepted at ICCAD 2015.
- April 2015: Consider submitting an abstract to TAPAS 2015.
- February 2015: Consider submitting a paper to EMSOFT 2015, which will take place in Amsterdam this year.
- October 2014: Our paper on topology analysis of graph transformation systems has been accepted at VMCAI 2015.
- October 2014: Our paper on A Compiler Optimization to Increase the Efficiency of WCET Analysis appears at RTNS 2014 and has been named an Outstanding Paper!
- June 2014: Randomized Caches Considered Harmful!
- January 2014: Our papers on Architecture-Parametric Timing Analysis and Selfish-LRU have been accepted at RTAS 2014.
- January 2014: Our paper on Basic Problems in Multi-View Modeling has been accepted at TACAS 2014.
- The survey about the impact of resource sharing on performance and performance prediction that we wrote as part of a doctoral privatissimum will appear in CONCUR 2013.
- June 2013: Our paper on the static analysis of cache side channels has been accepted at USENIX Security 2013.
- April 2013: Jan gave an Intel Tech Talk at Intel Braunschweig on challenges for WCET analysis of contemporary microarchitectures.
- August 2012: Jan Reineke has received an Intel Early Career Faculty Award!