Cropped version of CC BY-NC image courtesy of Inge Johnsson.

Welcome to WCET 2017

The 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017) is a satellite workshop of the 29th Euromicro Conference on Real-Time Systems (ECRTS 2017), the premier European venue for research in the broad area of real-time and embedded systems.

In 2017, the WCET workshop and ECRTS will be held in the beautiful city of Dubrovnik, Croatia.

Important Dates

  • Paper Submission deadline (extended!): April 14, 2017 (23:59 anywhere on earth) (March 31, 2017)
  • Notification of acceptance: May 8, 2017
  • Conference and workshops early registration deadline: May 12, 2017
  • Camera-ready version deadline (extended!): May 22, 2017 (May 15, 2017)
  • WCET Workshop: June 27, 2017
  • ECRTS Conference: June 28-30, 2017

Submission Portal

Please submit your paper via EasyChair following this link.

Submission instructions can be found below.

Goals and Topics

A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multi-threading, which introduce a large degree of uncertainty and make timing guarantees harder to provide.

The WCET workshop focuses on the analysis and design of timing-predictable systems, with a strong emphasis on worst-case execution time (WCET) analysis. Topics of interest include all aspects of timing analysis and timing predictability. This includes, but is not limited to:

  • Integration of WCET and schedulability analysis
  • Processor and hardware design for timing predictability
  • Program design for timing predictability
  • WCET analysis for multi-threaded and multi-core systems
  • Low-level timing analysis, modeling and analysis of processor features
  • Flow analysis for WCET, loop bounds, infeasible paths
  • Measurement-based WCET analysis
  • Tools for WCET analysis
  • Integration of WCET analysis in development processes
  • Strategies to reduce the complexity of WCET analysis
  • Compiler-based optimization of worst-case timing
  • Timing-predictable, resource-aware operating systems
  • Experimental analysis of the timing behavior of processors
  • Methods and benchmarks for WCET analysis evaluation
  • Case studies and industrial experiences of WCET analysis
  • WCET analysis in the academic curriculum
Statements which are innovative, controversial, or that present new approaches are specially sought.

Workshop Structure

The goal of the workshop is to bring together people from academia, tool vendors and users in industry who are interested in all aspects of timing predictability of real-time systems. The workshop fosters a highly interactive format with ample time for in-depth discussions. It provides a relaxed forum to present and discuss new ideas, new research directions, and to review current trends in this area. The presentations will be kept short to leave plenty of time for interaction of attendees.

Submission Instructions

Research papers should present original research results not published or submitted for publication in other forums. Accepted papers will be published via Schloss Dagstuhl's OASIcs online proceedings series. By submitting a paper, the authors agree and confirm that: 1. Neither this paper, nor a version close to it, is under submission or will be submitted elsewhere before notification by WCET 2017. 2. If accepted, at least one author will register for WCET 2017, and present the paper at the workshop in person.

Papers submitted for the WCET workshop must be written in English, must not exceed 10 pages, should conform with the OASIcs typesetting requirements, and must be submitted in PDF format using the WCET workshop paper submission website. Author names, affiliations and self-references should not be anonymized.

Program Chair

Jan Reineke
Saarland University, Germany

Program Committee

Sebastian Altmeyer
University of Amsterdam, Netherlands

Clement Ballabriga
Lille 1 University, France

Florian Brandner
Telecom ParisTech, France

Hugues Cassé
IRIT - Université de Toulouse, France

Francisco J. Cazorla
Barcelona Supercomputing Center, Spain

Heiko Falk
Hamburg University of Technology, Germany

Niklas Holsti
Tidorum Ltd, Finland

Claire Maiza
Grenoble INP/Verimag, France

Kartik Nagar
Purdue University, United States

Luis Miguel Pinho
CISTER Research Centre/ISEP, Portugal

Dumitru Potop Butucaru
INRIA Rocquencourt, France

Wolfgang Puffitsch
Oticon A/S, Denmark

Peter Puschner
Vienna University of Technology, Austria

Martin Schoeberl
Technical University of Denmark, Denmark

Benoit Triquet
Airbus Group, France

Steering Committee

Guillem Bernat
Rapita Systems Ltd., UK

Björn Lisper
Mälardalen University, Sweden

Isabelle Puaut
University of Rennes I/IRISA, France

Peter Puschner
Vienna University of Technology, Austria

Previous Editions

WCET 2016

WCET 2015

WCET 2014

WCET 2013

WCET 2012

WCET 2011