SafeSecS: Abstractions for Safe and Secure Hardware-Software Systems

We are constantly looking for PhD students and postdocs to work on safety and security problems at the hardware-software interface!
Possible research topics are flexible and include but are not limited to:
  • Static program analysis of real-time and security properties
  • Design of timing-predictable microarchitectures
  • Design of secure microarchitectures
  • Formal verification of hardware w.r.t. hardware-software contracts
If you are interested, please feel free to . The SafeSecS project is generously supported by an ERC Advanced Grant.

We are also looking for student research assistants.
If you are interested in working with me and my group or if you are looking for a Bachelor or Master thesis topic, please feel free to stop by my office or to drop me an .

Motivation

Trains, planes, and other safety- and security-critical systems that our society relies on are controlled by computer systems, as is much of our critical infrastructure, including the power grid and cellular networks. But can we trust in the safety and security of these systems?

The starting point of SafeSecS is the observation that today’s hardware-software abstractions, instruction set architectures (ISAs), are fundamentally inadequate for the development of safe or secure systems. Indeed, ISAs abstract from timing, making it impossible to develop safety-critical systems that have to satisfy real-time constraints on top of them. Neither do ISAs provide sufficient security guarantees, making it impossible to develop secure systems on top of them. As a consequence, engineers are forced to rely on brittle timing and security models that are proven wrong time and again, as evidenced e.g. by the recent Spectre attacks; putting our society at risk.

SafeSecS attacks the problem at its root by introducing a framework centered around hardware-software contracts that extend the guarantees provided by ISAs to capture key non-functional properties. Hardware-software contracts formally capture the expectations on correct hardware implementations and they lay the foundation for achieving safety and security guarantees as the software level. Below the hardware-software interface, SafeSecS aims to contribute modular design principles and tools to construct microarchitectures that provably satisfy a given hardware-software contract. Above the hardware-software interface, SafeSecS will develop rigorous, precise, and scalable techniques to guarantee key safety and security properties at the software level on top of hardware-software contracts. As a whole, SafeSecS will enable the systematic engineering of safe and secure hardware-software systems we can trust in.

Relevant Publications

Journal Papers

  1. Type-aware Federated Scheduling for Typed DAG Tasks on Heterogeneous Multicore Platforms
    C. Lin, J. Shi, N. Ueter, M. Günzel, J. Reineke, and J. Chen
    IEEE Trans. Computers, 72(5), 2023
    [doi] [bib]

Conference and Workshop Papers

  1. Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors (Best Paper Award Candidate award)
    G. Mohr, M. Guarnieri, and J. Reineke
    DATE, March 2024
    [bib]
  2. Kawa: An Abstract Language for Scalable and Variable Detection of Spectre Vulnerabilities (Third Place in SPLASH 2024 Student Research Competitionaward)
    Z. Wu, H. Zeng, and A. Bies
    Companion Proceedings of the 2024 ACM SIGPLAN International Conference on Systems, Programming, Languages, and Applications: Software for Humanity, 2024
    [doi] [bib]
  3. FACILE: Fast, Accurate, and Interpretable Basic-Block Throughput Prediction
    A. Abel, S. Sharma, and J. Reineke
    IISWC, 2023
    [doi] [bib]
  4. Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis (Outstanding Paper Award award)
    V. Touzeau and J. Reineke
    RTSS, 2023
    [bib]
  5. Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts (Distinguished Paper Award at CCS 2023 and Intel Hardware Security Academic Award Finalist 2024award)
    Z. Wang, G. Mohr, K. Gleissenthall, J. Reineke, and M. Guarnieri
    CCS, 2023
    [bib]
  6. uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
    A. Abel and J. Reineke
    ICS, 2022
    [bib]
  7. LLVMTA: An LLVM-Based WCET Analysis Tool
    S. Hahn, M. Jacobs, N. Hölscher, K. Chen, J. Chen, and J. Reineke
    WCET, 2022
    [doi] [bib]
  8. Warping Cache Simulation of Polyhedral Programs
    C. Morelli and J. Reineke
    PLDI, June 2022
    [doi] [bib]
  9. On the Trade-offs between Generalization and Specialization in Real-Time Systems
    G. der Brüggen, A. Burns, J. Chen, R. Davis, and J. Reineke
    RTCSA, 2022
    [bib]
  10. Hardware-Software Contracts for Secure Speculation (Best Paper Award award)
    M. Guarnieri, B. Köpf, J. Reineke, and P. Vila
    S&P (Oakland), May 2021
    [bib]